std_logic_vector representing one bit

[ALuPin]

Hi,

I have the following problem, maybe I am to blind to see
the solution )


signal declaration:

signal li3_q : std_logic_vector(0 downto 0);

The signal was created that way when instantiating a RAM component.

How can I do an if-then-else?


if li3_q='1' then
...
else
....
end if;

The compiler (Altera QuartusII) says:
"Error: VHDL error at ... : can't determine definition of operator "="
-- found 0 possible definitions"

Would be thankful for any explanation.

Kind regards

Andrés V.

 

[valentin tihomirov]

Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
=> '1').

 

[Egbert Molenkamp]

It is a vector .. so you should treat it as a vector : if li3_q="1"
or if li3_q(0)='1'

Egbert Molenkamp


"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0402250534.463aeb22@posting.google.com...

Hi,

I have the following problem, maybe I am to blind to see
the solution )


signal declaration:

signal li3_q : std_logic_vector(0 downto 0);

The signal was created that way when instantiating a RAM component.

How can I do an if-then-else?


if li3_q='1' then
...
else
....
end if;

The compiler (Altera QuartusII) says:
"Error: VHDL error at ... : can't determine definition of operator "="
-- found 0 possible definitions"

Would be thankful for any explanation.

Kind regards

Andrés V.

 

[Egbert Molenkamp]

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> schreef in
bericht news:c1i8mg$1jaanc$1@ID-212430.news.uni-berlin.de...

Vector is not the same as a signal. Try if VEC = "1" then or VEC = (others
=> '1').

if VEC = (others => '1') then ..

is not correct. Correct is:

if VEC=(VEC'RANGE=>'1') then
(but I'm not sure if MaxPlus supports this).

Egbert Molenkamp