std_logic_vector divide

[Ciar?n Hughes]

Hi all,

Is there any operator to divide a std_logic_vector, either by another
std_logic_vector or by an integer?

I am using the following code at the moment

temp := CONV_INTEGER(buf2) / q ;
ZRLOut <= CONV_STD_LOGIC_VECTOR(temp,11);

where buf2 and ZRLOut are signals of type std_logic_vector, temp is a
variable of type integer, and q is a signal of type integer.

Thanks
Ciarán Hughes

This works fine in behavioural simulation, but when I run a post
translate simulation, the division seems to be ignored, i.e. ZRLOut is
equal buf2. It is like the division can't be synthesised, and is
ignored (like the after statement).

Thanks,
Ciarán Hughes

 

[FE]

Sorry, division operator are not available for synthesis, except for power
of 2 (shift).You must design it. You can check for non restoring algorithm
on the web (I think that it's the easiest algorithm to implement) and you
can found some existing vhdl implemetation too.

regards
fe

"Ciar?n Hughes" <ciaran.hughes@nuigalway.ie> wrote in message
news:30099b05.0310010105.79df0d5e@posting.google.com...

Hi all,

Is there any operator to divide a std_logic_vector, either by another
std_logic_vector or by an integer?

I am using the following code at the moment

temp := CONV_INTEGER(buf2) / q ;
ZRLOut <= CONV_STD_LOGIC_VECTOR(temp,11);

where buf2 and ZRLOut are signals of type std_logic_vector, temp is a
variable of type integer, and q is a signal of type integer.

Thanks
Ciarán Hughes

This works fine in behavioural simulation, but when I run a post
translate simulation, the division seems to be ignored, i.e. ZRLOut is
equal buf2. It is like the division can't be synthesised, and is
ignored (like the after statement).

Thanks,
Ciarán Hughes

 

[David Bishop]

You will find an unsigned divide routine commented out in
the floating point routines.

http://www.eda.org/fphdl/vhdl/fphdl_base_pkg_body.vhd

It is done as a subtraction tree, not very elegant, but it will
synthesize.

Ciar?n Hughes wrote:

Hi all,

Is there any operator to divide a std_logic_vector, either by another
std_logic_vector or by an integer?

I am using the following code at the moment

temp := CONV_INTEGER(buf2) / q ;
ZRLOut <= CONV_STD_LOGIC_VECTOR(temp,11);

where buf2 and ZRLOut are signals of type std_logic_vector, temp is a
variable of type integer, and q is a signal of type integer.

Thanks
Ciarán Hughes

This works fine in behavioural simulation, but when I run a post
translate simulation, the division seems to be ignored, i.e. ZRLOut is
equal buf2. It is like the division can't be synthesised, and is
ignored (like the after statement).

Thanks,
Ciarán Hughes

--
NAME: David W. Bishop INTERNET: dbishop@nospamvhdl.org