std_logic_vector cosmetic

[Olaf Petzold]

Hi,

this time a question concerning a cosmetic change. I assign a
subvector/slice with leading zero to a new one like this way:

foo : std_logic_vector(7 downto 0);
bar : std_logic_vector(15 downto 0);

.....
constant ZERO_PAD : std_logic_vector(5 downto 0) := (others => '0');

.....

foo <= ZERO_PAD & bar(1 downto 0);

Is there a better way avoiding the ZERO_PAD constant, like

foo <= (1,2 => bar(1 downto 0), others => '0');

which doesn't compile?:

Type conflict in integer literal. (Type 'std_logic' versus 'integer'.)
Cannot resolve slice name as type std_logic.
Associations in array aggregate must be all named or all positional.

Thanks
Olaf

 

[Mike Treseler]

Olaf Petzold wrote:

Is there a better way avoiding the ZERO_PAD constant

Nothing better really.
This is how I would do it:

foo_v := (foo'range => '0'); -- zero fill
foo_v(1 downto 0) := bar(1 downto 0); -- fix two bits
foo <= foo_v; -- out to port

-- Mike Treseler

-------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity pad is
port (foo : out std_logic_vector(7 downto 0));
end entity pad;

architecture sim of pad is
begin
one: process is
constant bar : std_logic_vector(15 downto 0):= x"aaaa";
variable foo_v : std_logic_vector(foo'range);
begin -- process one
foo_v := (foo'range => '0'); -- zero fill
foo_v(1 downto 0) := bar(1 downto 0); -- fix two bits
assert foo_v = x"02" report "unexpected value for foo_v";
report "No assertions expected above.";
foo <= foo_v; -- out to port
-- Thu Oct 20 14:37:09 2005 Mike Treseler
wait;
end process one;

end architecture sim;
------------------------------------------------------------------
--# vsim -c pad
--# Loading /steptoe/usr1/modeltech/linux/../std.standard
--# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
--# Loading work.pad(sim)
--VSIM 1> run
--# ** Note: No assertions expected above.
--# Time: 0 ns Iteration: 0 Instance: /pad
--VSIM 2>

 

[Mark McDougall]

Olaf Petzold wrote:

foo <= ZERO_PAD & bar(1 downto 0);

Is there a better way avoiding the ZERO_PAD constant, like
foo <= (1,2 => bar(1 downto 0), others => '0');

foo <= EXT(bar(1 downto 0), 8);

Regards,
Mark

 

[Benjamin Todd]

What does the function EXT do exactly?

"Mark McDougall" <markm@vl.com.au> wrote in message
news:43583ec5$0$28022$5a62ac22@per-qv1-newsreader-01.iinet.net.au...

Olaf Petzold wrote:

foo <= ZERO_PAD & bar(1 downto 0);

Is there a better way avoiding the ZERO_PAD constant, like
foo <= (1,2 => bar(1 downto 0), others => '0');

foo <= EXT(bar(1 downto 0), 8);

Regards,
Mark

 

[Olaf Petzold]

Benjamin Todd schrieb:

What does the function EXT do exactly?

-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return
STD_LOGIC_VECTOR;


see http://www.csee.umbc.edu/help/VHDL/std_logic_arith_syn.vhdl

Regards,
Olaf

 

[Benjamin Todd]

Cheers!
"Olaf Petzold" <olaf@mdcc-fun.net> wrote in message
news:djbdm1$qeo$1@viper.mdlink.de...

Benjamin Todd schrieb:
What does the function EXT do exactly?

-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return
STD_LOGIC_VECTOR;


see http://www.csee.umbc.edu/help/VHDL/std_logic_arith_syn.vhdl

Regards,
Olaf

 

[Andy Peters]

Olaf Petzold wrote:

Benjamin Todd schrieb:
What does the function EXT do exactly?

-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return
STD_LOGIC_VECTOR;


see http://www.csee.umbc.edu/help/VHDL/std_logic_arith_syn.vhdl

Alternatively, and preferably, one can use resize() in numeric_std.

(It's been fifteen minutes since there was a post advocating
numeric_std over std_logic_arith, so I figured I'd do my part ...)

-a

 

[Mike Treseler]

Andy Peters wrote:

(It's been fifteen minutes since there was a post advocating
numeric_std over std_logic_arith, so I figured I'd do my part ...)

Way to lean in and take one for the team

-- Mike Treseler

http://groups.google.com/groups?q=vhdl+resize+msb+carry