std_logic_vector(0 downto 0)

[Brad Smallridge]

The Xilinx core generator generates std_logic_vector(0 downto 0) on some
parts like a BUSMUX. How do you "cast" this IO so that it can be connected
to std_logic without errors?

Brad Smallridge
b r a d @ a i v i s i o n . c o m

 

[Antti Lukats]

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10p9p836ut3ila4@corp.supernews.com...

The Xilinx core generator generates std_logic_vector(0 downto 0) on some
parts like a BUSMUX. How do you "cast" this IO so that it can be
connected
to std_logic without errors?

Brad Smallridge
b r a d @ a i v i s i o n . c o m

signal_not_vector <= signal_vector_size0(0);

maybe there is other way, but I do the above if needed.
Antti

 

[Michael Riepe]

Hi!

Andrea Sabatini wrote:

a : std_logic_vector(0 downto 0) ;
b : std_logic ;
[...]
b <= a(0) ;

Alternatively:

(0 => b) <= a;

(choose whichever seems more appropriate). Similarly, if `a' is a port,
you can use individual association:

a(0) => b

or associate the port as a whole:

a => (0 => b)

in the port map aspect of the component instantiation statement.

--
Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
"All I wanna do is have a little fun before I die"

 

[Andrea Sabatini]

Brad,

if

a : std_logic_vector(0 downto 0) ;

and

b : std_logic ;

then

b <= a(0) ;

Hope this help,

Andrea


"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10p9p836ut3ila4@corp.supernews.com...

The Xilinx core generator generates std_logic_vector(0 downto 0) on some
parts like a BUSMUX. How do you "cast" this IO so that it can be
connected
to std_logic without errors?

Brad Smallridge
b r a d @ a i v i s i o n . c o m