std_logic_arith / numeric_std

[ALuPin]

Hi,

let's assume the following thing:

In my toplevel-module I use the
"ieee.std_logic_arith.all" library

In a submodule I use the
"ieee.numeric_std.all" library for the purpose
of realizing a barrel shifter.


My question: Is that some kind of confusion for
the synthesis tool when performing synthesis?

I would appreciate your help.

Thank you very much.

Kind regards
Andres V.

 

[Amontec Team]

ALuPin wrote:

Hi,

let's assume the following thing:

In my toplevel-module I use the
"ieee.std_logic_arith.all" library

In a submodule I use the
"ieee.numeric_std.all" library for the purpose
of realizing a barrel shifter.


My question: Is that some kind of confusion for
the synthesis tool when performing synthesis?

I would appreciate your help.

Thank you very much.

Kind regards
Andres V.

Yes we know the trouble. It is coming from multiple function description
for the same function declaration.
We do not use *NEVER* "ieee.std_logic_arith.all" library for
synthesizable component.

Please use exclusively ieee.numeric_std.all.

Laurent,
www.amontec.com

 

[Jim Lewis]

Amontec Team wrote:

Yes we know the trouble. It is coming from multiple function description
for the same function declaration.
We do not use *NEVER* "ieee.std_logic_arith.all" library for
synthesizable component.

I agree with this statement, but it does not sound like it
matches the question.

If the interfaces are std_logic/std_logic_vector and
unsigned/signed are used only internally, then from a VHDL
perspective it is ok to use std_logic_arith and
numeric_std in different entities in the design.
My only concern, probably matching that of yours, is that I
have not tried this with any synthesis tools.

Please use exclusively ieee.numeric_std.all.

This I agree with. However, I do have to admit
that I also use std_logic_unsigned and will continue
until the 1076.3 creates and standardizes an unsigned
version of numeric_std. My motivation is more for
testbenches than for rtl code though.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[paris]

"ALuPin" <ALuPin@web.de> escribió en el mensaje
news:b8a9a7b0.0404060302.398eb2@posting.google.com...

Hi,

let's assume the following thing:

In my toplevel-module I use the
"ieee.std_logic_arith.all" library

In a submodule I use the
"ieee.numeric_std.all" library for the purpose
of realizing a barrel shifter.


My question: Is that some kind of confusion for
the synthesis tool when performing synthesis?

I would appreciate your help.

Thank you very much.

Kind regards
Andres V.

i believe the library selection (keywords, "library" and "use") have only
local scope, meaning that they apply only to the entity and architecture
just below them. If you have more than one entity and architecture in a
single file, you have to redeclare "library" and "use" just before a new
entity (i believe it's like that, maybe it's like if you dont redeclare
them, it means you want to use the ones you indicated in the first place).
In anycase the result is (if my memory doesnt fail) that each module has
it's own dependencies.

 

[paris]

"Amontec Team" <laurent.gauch@amontec.com> escribió en el mensaje
news:4072C302.6010405@amontec.com...

ALuPin wrote:
Hi,

let's assume the following thing:

In my toplevel-module I use the
"ieee.std_logic_arith.all" library

In a submodule I use the
"ieee.numeric_std.all" library for the purpose
of realizing a barrel shifter.


My question: Is that some kind of confusion for
the synthesis tool when performing synthesis?

I would appreciate your help.

Thank you very much.

Kind regards
Andres V.

Yes we know the trouble. It is coming from multiple function description
for the same function declaration.
We do not use *NEVER* "ieee.std_logic_arith.all" library for
synthesizable component.

Please use exclusively ieee.numeric_std.all.

exactly, but i've always seen the "std_logic_arith" and "std_logic_signed"
thingy in all the sources i've come across, and when i've wrote a module
with "numeric_std" people told me to use "arith" and "signed"!?! what's
going on?
maybe in ASIC is more like "numeric_std" and in the FPGA world is more like
a "arith" and "signed" thing??!

 

[Tim Hubberstey]

paris wrote:

... i've always seen the "std_logic_arith" and "std_logic_signed"
thingy in all the sources i've come across, and when i've wrote a module
with "numeric_std" people told me to use "arith" and "signed"!?! what's
going on?

The problem with std_logic_arith is that it is implemented differently
by different synthesis vendors. However, it was the standard in the days
prior to the existence (and support for) numeric_std. As a result, many
companies have standardized on std_logic_arith (usually the Synopsys
flavour) in order to promote code re-use. These companies often have a
truly huge investment in their synthesis tools, and their code base, and
it would take an Act of God to get them to change; hence, they don't
care about potential incompatibilities. They discourage use of
numeric_std because they do not want to lose the ability to snip chunks
of code out of older modules and paste into new projects.

maybe in ASIC is more like "numeric_std" and in the FPGA world is
more like
a "arith" and "signed" thing??!

Actually, it's most likely the other way around. ASIC synthesis tools
were very slow to adopt support for numeric_std.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com