C
Chris
Guest
I'm hoping someone out there can help me.
We've been having lots of trouble closing the timing on our FPGAs with
our bespoke vendor supplied static timing analysis tool.
Is anyone out there using a stand alone static timing analysis tool
(other than Primetime from Synopsys, or anything supplied by the FPGA
vendors)?
What is it? How do you find using it? What was the learning curve
like?
We've been having lots of trouble closing the timing on our FPGAs with
our bespoke vendor supplied static timing analysis tool.
Is anyone out there using a stand alone static timing analysis tool
(other than Primetime from Synopsys, or anything supplied by the FPGA
vendors)?
What is it? How do you find using it? What was the learning curve
like?