Static options for Case Statement

[dwerdna]

Hello all

Im getting a warning in Modelsim saying that my case statement options
needs to be static

ie

case test is
when 1 =>
when 2 =>
when 3 =>
end case;

would be a static statement..

Now what I have is a set of constants instead of explicit values

constant C_ONE : integer := 1;
etc, etc

case test is
when C_ONE =>
when C_TWO =>
when C_THREE =>
end case;

now that usually works fine for me, except in this case my constant is
a derived value from other constants

constant C_IRDA_CMD_NUM_0_VEC : std_logic_vector(C_IRDA_CMD_WIDTH - 1
downto 0) :=
std_logic_vector(to_unsigned(C_IRDA_CMD_NUM_0,C_IRDA_CMD_WIDTH));


(im converting a constant that is declared as an integer into a
std_logic_vector so to be able to match on a field in a pkt)

I usually have all my constants in a pkg_constants.vhd file, and I have
also tried to move it locally and declare it in the source file it will
be used in, and these warnings still come up. The issue I have is by
definition constants are static!!!

Its only a warning, so maybe it doesn't matter, and I haven't
actually got to looking at this section of code in the simulation, and
it could be a modelsim translation issue, rather than my own fault.. I
just don't know.. I seem to be doing the right thing, as my text
book suggests, and I'm compiling the pkg file before the source file
and all that...

Any ideas?

Thanks

 

[Mike Treseler]

dwerdna wrote:

Hello all

Im getting a warning in Modelsim saying that my case statement options
needs to be static

This has be discussed here. See:
http://groups-beta.google.com/groups?q=vhdl+case+static

-- Mike Treseler

 

[dwerdna]

OK, thanks!