Static Noise Margin Simulation

R

rajshri

Guest
Hi,
I am simulating the logic cells for static noise margin using
standard simulation method used for SRAM cells. I have two indepenednt
circuits getting simulated in the same schematic. I am using VCVS in my
circuits. I am observing one circuit affecting on the other! Have any
one experinced this while doing this kind of simulations? I can explain
my problem better if anyone have experience with SNM simulation.
Thanks,
Rajashri
 
On 12 Sep 2006 16:04:16 -0700, "rajshri" <susnithakiran@yahoo.co.in>
wrote:

Hi,
I am simulating the logic cells for static noise margin using
standard simulation method used for SRAM cells. I have two indepenednt
circuits getting simulated in the same schematic. I am using VCVS in my
circuits. I am observing one circuit affecting on the other! Have any
one experinced this while doing this kind of simulations? I can explain
my problem better if anyone have experience with SNM simulation.
Thanks,
Rajashri
Click to expand...
I can think of a variety of setups to measure static noise margins.

Please post a URL link to a schematic.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
Hi,
I am using the schematic posted in this paper.
E. Seevinck, et al, "Static-Noise Margin Analysis of MOS SRAM
Cells", IEEE J.
of Solid-State Circuits, Vol. SC22, No. 5, p.p.748-754, 1987.
I am simulating for master latch and slave latch. Though the
circuits are indepenedent of each other except power and ground, the
results are getting mixed up!
Thanks,
Rajashri

Jim Thompson wrote:

On 12 Sep 2006 16:04:16 -0700, "rajshri" <susnithakiran@yahoo.co.in
wrote:

Hi,
I am simulating the logic cells for static noise margin using
standard simulation method used for SRAM cells. I have two indepenednt
circuits getting simulated in the same schematic. I am using VCVS in my
circuits. I am observing one circuit affecting on the other! Have any
one experinced this while doing this kind of simulations? I can explain
my problem better if anyone have experience with SNM simulation.
Thanks,
Rajashri

I can think of a variety of setups to measure static noise margins.

Please post a URL link to a schematic.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
Click to expand...
 
On 13 Sep 2006 07:27:35 -0700, "rajshri" <susnithakiran@yahoo.co.in>
wrote:

Hi,
I am using the schematic posted in this paper.
E. Seevinck, et al, "Static-Noise Margin Analysis of MOS SRAM
Cells", IEEE J.
of Solid-State Circuits, Vol. SC22, No. 5, p.p.748-754, 1987.
I am simulating for master latch and slave latch. Though the
circuits are indepenedent of each other except power and ground, the
results are getting mixed up!
Thanks,
Rajashri

[snip]
Click to expand...

My JSSC saved papers only go back to 1997.

Post your schematic.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
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