state machine without clock

Miller2000 · May 9, 2005

I try to implement state machine without clock.
Theâ âinputsâ
ââ(âlatchâ8ââ,âlatchâ8âtagâ,âlatchâ1ââ6ââ)ââ
âareâ âchangingâ âtheâ âstateâ â
withoutâ âclockâ.â

I still get error:

ERROR:Xst:2089 - "sm1.v" line 48:
This sensitivity list construct will match none of the supported FF or
Latch templates.

Please Help!
miller2000

==================The code:
==================
module sm1(in8, latch8, latch8tag, latch16, reset, out16);
input [7:0] in8;
input latch8;
input latch8tag;
input latch16;
input reset;
output [15:0] out16;

wire [7:0] in8;
wire reset;
wire latch8;
wire latch8tag;
wire latch16;

reg [15:0] out16;
reg [7:0] ff1;
reg [7:0] ff2;

wire temp1;
wire temp2;

reg [1:0] state;

parameter zero=0, one=1, two=2;

assign temp1 = latch8 ^ latch8tag;
assign temp2 = ~(latch8 ^ latch8tag);
always @(negedge temp1 or negedge temp2 or
posedge latch16 or posedge reset)
begin
if(reset)
begin
out16<=0;
ff1<=0;
ff2<=0;
state<= zero;
end
else
if(state==zero)
begin
ff1<=in8;
state<= one;
end
else
if(state==one)
begin
ff2<=in8;
state<= two;
end
else
if(state==two)
begin
out16<={ff1,ff2};
state<= zero;
end
end
endmodule

chainastole · May 9, 2005

1) latch16 isn't used in design.
2) what are you doing with temp1, temp2?
3) why temp1, temp2, latch16 appear in the sensitivity list - they
aren't used in any logic.
4) ff1,ff2, in8 don't appear in the sensitivity list, but they are used
ander always.

I suppose that the given logic describes any state machine logic, which
is further (where the module is instantiated) should be sampled to ff.
I would recommend to extract the reset logic from the module and place
it in this ff description in some following form.

always @ (posedge clk or posedge reset) begin
if(reset)
out16_s <= 1'd0;
else out16_s <= out16;
end

This form is proven as the form, which is interpreted by compiler as
the FF.

Miller2000 · May 9, 2005

The gool of the program is:
Latch input 8 bits at "posedge of latch8" OR "negedge of latch8tag"
and put it in FF1.
Latch input 8 bits at "negedge of latch8" OR "posedge of latch8tag"
and put it in FF2.
Output FF1 + FF2 to output 16 bits at "posedge of latch16".

There is no clock in the system!

Miller2000 · May 9, 2005

I try another aprouch, without State machine, and have the same error :

ERROR:Xst:899 - "sm1.v" line 42: The logic for <ff1> does not match a
known FF or Latch template.

=====================
The code:
=====================
module sm1(in8, latch8, latch8tag, latch16, reset, out16);
input [7:0] in8;
input latch8;
input latch8tag;
input latch16;
input reset;
output [15:0] out16;

wire [7:0] in8;
wire reset;
wire latch8;
wire latch8tag;
wire latch16;

reg [15:0] out16;
reg [7:0] ff1;
reg [7:0] ff2;

always @ (posedge latch8 or negedge latch8tag or posedge reset)
begin
if(reset)
ff1 <= 8'd0;
else
ff1 <= in8;
end

always @ (posedge latch8tag or negedge latch8 or posedge reset)
begin
if(reset)
ff2 <= 8'd0;
else
ff2 <= in8;
end

always @ (posedge latch16 or posedge reset)
begin
if(reset)
out16 <= 8'd0;
else
out16 <= {ff1,ff2} ;
end

endmodule

Miller2000 · May 9, 2005

Hi Mike!

Theâ âcustomerâ âwantsâ âthatâ âthereâ âwillâ
âbeâ ânoâ ââ"âclockâ"ââ.â

Iâ âwantâ âtoâ âlatchâ ââ"âinputâ ââ8ââ
âbitâ"ââ âintoâ âaâ âflipâ-âflopâ âwhenâ
ââ"âposedgeâ âofâ âlatchâ8ââ"ââ âORâ
ââ"ânegedgeâ âofâ âlatchâ8âtagâ"ââ ââ,â
soâ âitâ âisâ âexternalâ âsignalâ âthatâ
âmakeâ âtheâ âlatchâ âtoâ âtheâ âflipâ
âflopâ.â

Isâ âitâ âimposableâ ââ?â

Thanks.
miller2000

Avrum · May 9, 2005

The error message is actually pretty explicit. It is telling you that it
cannot recognize the code you have written as a flip-flop (or a latch, for
that matter).

What you have coded, in fact, does not correspond to any real hardware
element; there is no hardware element that has two different clocking
mechanisms; a (normal) flip flop has one "active edge" that clocks the
element, it may be either the rising or falling edge of a single signal,
therefore the "@(posedge latch8 or negedge latch8tag)" is an impossible
clocking condition from the point of view of a hardware element.

Your description of the desired behaviour is not complete, and hence no one
can suggest the "correct" coding for your problem. You are asking for things
to happen on 4 different edges of two signals. Since you are only trying to
do two things on these 4 edges (capture the upper 8 bits or capture the
lower 8 bits), it is POSSIBLE that there may be a way to combine the two
edges for each condition together to create the proper single edge for the
clock for the flip-flops. For example, creating a signal (latch8 ^
latch8tag) and clocking ff1 on the rising edge of this combined signal, and
ff2 on the falling edge MAY do what you want, depending on the relationship
between these two signals.

That being said, what you are trying to do sounds like either a
misunderstanding of the requirements, or just plain a bad idea....

I can imagine two different scenarios that make a little sense...

1) capture the most significant 8 bits on the rising edge of latch8, capture
the least significant bits on the falling edge of latch8, and the
concatenate the two together on latch16. This would look like a relatively
normal double data rate type protocol

2) capture the most significant 8 bits on the risigne edge of latch8 and the
least significant bits on the rising edge of latch8tag, and then concatenate
the two together on latch16. This looks similar to the protocol on some
older style multiplexed busses that give you a strobe for both phases.

Separately, the two cases make sense, and can be coded (and synthesized).
What you are describing seems to be some odd combination of the two, which
(without a much better understanding of the relationship between latch8 and
latch8tag) cannot be implemented.

Avrum

"Miller2000" <miller2000@walla.com> wrote in message
news:1115645687.675188.206050@z14g2000cwz.googlegroups.com...

I try another aprouch, without State machine, and have the same error :

ERROR:Xst:899 - "sm1.v" line 42: The logic for <ff1> does not match a
known FF or Latch template.

=====================
The code:
=====================
module sm1(in8, latch8, latch8tag, latch16, reset, out16);
input [7:0] in8;
input latch8;
input latch8tag;
input latch16;
input reset;
output [15:0] out16;

wire [7:0] in8;
wire reset;
wire latch8;
wire latch8tag;
wire latch16;

reg [15:0] out16;
reg [7:0] ff1;
reg [7:0] ff2;

always @ (posedge latch8 or negedge latch8tag or posedge reset)
begin
if(reset)
ff1 <= 8'd0;
else
ff1 <= in8;
end

always @ (posedge latch8tag or negedge latch8 or posedge reset)
begin
if(reset)
ff2 <= 8'd0;
else
ff2 <= in8;
end

always @ (posedge latch16 or posedge reset)
begin
if(reset)
out16 <= 8'd0;
else
out16 <= {ff1,ff2} ;
end

endmodule

Miller2000 · May 9, 2005

Hiâ âAvrumâ ââ!â

Tanksâ âforâ âtheâ âreplayâ.â

Whatâ âtheâ âcustomerâ âwantsâ âisâ âyourâ
âoptionâ ââ1ââ:â
â1ââ)ââ âcaptureâ âtheâ âmostâ âsignificantâ
ââ8ââ âbitsâ âonâ âtheâ ârisingâ âedgeâ
âofâ âlatchâ8ââ,ââ âcaptureâ â
theâ âleastâ âsignificantâ âbitsâ âonâ âtheâ
âfallingâ âedgeâ âofâ âlatchâ8ââ,ââ âandâ
âtheâ â
concatenateâ âtheâ âtwoâ âtogetherâ âonâ
âlatchâ1ââ6ââ.ââ âThisâ âwouldâ âlookâ
âlikeâ âaâ ârelativelyâ â
normalâ âdoubleâ âdataâ ârateâ âtypeâ âprotocolâ
â

BUTâ âtheâ âcustomerâ âwantsâ âthatâ âheâ
âhaveâ âanâ âoptionâ âtoâ âdoâ âtheâ âsameâ
âasâ ââ(ââ1ââ)â
withâ âlatchâ8âtagâ âthatâ âitâ âisâ âtheâ
âactivateâ âoppositeâ:ââ ââ"âfallingâ âedgeâ
âofâ âlatchâ8âtagâ"ââ âthenâ ââ"ârisingâ
âedgeâ âofâ âlatchâ8âtagâ"â

Theâ âcustomerâ âwillâ ânotâ âuseâ
âlatchâ8ââ âandâ âlatchâ8âtagâ âtogetherâ!â

Thatâââsâ âtheâ âreasonâ âIâ âuseâ
âtempâ1ââ â&â âtempâ2ââ ââ:ââ
ââ(âXORâ âtheâ âtwoâ âlatchesâ)â
â âassignâ âtempâ1ââ ââ=ââ âlatchâ8ââ
ââ^ââ âlatchâ8âtagâ;ââ â
â âassignâ âtempâ2ââ ââ=ââ
ââ~ââ(âlatchâ8ââ ââ^ââ
âlatchâ8âtagâ)ââ;ââ â
â âalwaysâ â@â(ânegedgeâ âtempâ1ââ âorâ
ânegedgeâ âtempâ2ââ ââ.ââ.ââ.ââ.â

Thanks
millerâ2ââ0ââ0ââ0â

Miller2000 · May 10, 2005

Hi Avrum!

Thanks again !

I got from the customer more requirements.
After latch the FF2 I will start external clock (implement with"shmit"
trigger) and start counter.
The counter after 1 count will put FF1+FF2 to out16 and
after 5 count make pulse out to "out_ldy" & "out_ldy_tag"

the problem is that I got warrning:

WARNING:Xst:905 - "sm1.v" line 94: The signals <result, out16, ff1,
ff2, out_ldy, out_ldy_tag> are missing in the sensitivity list of
always block.

Please Help!
Thanks
miller2000
=====================
The Code:
=====================
module sm1(in8, latch8, latch8tag, clk, reset, out_clk, out_ldy,
out_ldy_tag,out16);
input [7:0] in8;
input latch8;
input latch8tag;
input clk;
input reset;
output out_clk;
output out_ldy;
output out_ldy_tag;
output [15:0] out16;

wire [7:0] in8;
wire reset;
wire latch8;
wire latch8tag;
wire latch16;
wire temp_clk;
wire clk;
wire counter_clk;
wire out_clk;

reg [15:0] out16;
reg [7:0] ff1;
reg [7:0] ff2;

reg [2:0] result;
reg counter_en;
reg counter_rst;
reg clk_en;
reg out_ldy;
reg out_ldy_tag;

always @(posedge reset)
begin
ff1 <= 0;
ff2 <= 0;
out16 <= 0;
counter_en=0;
counter_rst=0;
clk_en=1;
result=0;
out_ldy=0;
out_ldy_tag=1;
end

assign temp_clk = (latch8 ^ ~latch8tag);

always @(negedge temp_clk)
ff1 <= in8;

always @(posedge temp_clk)
begin
ff2 <= in8;
counter_rst<=1;
clk_en<=0;
end

assign counter_clk = ~(clk | clk_en);
assign out_clk=counter_clk;

always @(posedge counter_clk or posedge counter_rst)
begin
if (counter_rst)
begin
result <= 0;
counter_rst=0;
end
else
if (counter_clk)
result <= result + 1;
end

always @(result or ff1 or ff2)
begin
if (result==1)
out16 <= {ff1,ff2};
else
if (result==5)
begin
out_ldy<=1;
out_ldy_tag<=0;
end
else
if (result==6)
begin
out_ldy<=0;
out_ldy_tag<=1;
clk_en<=1;
counter_rst<=1;
end
end

endmodule

Miller2000 · May 11, 2005

Hi John!
Thanks for the replay.

I fixed the "reset" by putting all "posedge reset" in all the always
that change the regs.

Instead of change the counter to "Gray counter", I put all the logic
inside of the counter.
Is it good approach?

Can I do always with posedge on reg instead of wire ?

About the exclusive-or in temp_clock it works as the customer wants
(I test it with modleSim and everything walk as I expected)

Now the problem now is that I got errors:

=========================================================================
* HDL Synthesis
*
=========================================================================
INFO:Xst:1304 - Contents of register <r_counter_rst> in unit <sm1>
never changes during circuit operation. The register is replaced by
logic.
INFO:Xst:1304 - Contents of register <clk_en> in unit <sm1> never
changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <sm1>.
Related source file is "sm1.v".
WARNING:Xst:2110 - Clock of register <result> seems to be also used in
the data or control logic of that element.
WARNING:Xst:2110 - Clock of register <out16> seems to be also used in
the data or control logic of that element.
WARNING:Xst:2110 - Clock of register <out_ldy> seems to be also used in
the data or control logic of that element.
WARNING:Xst:2110 - Clock of register <out_ldy_tag> seems to be also
used in the data or control logic of that element.

======================
The New code:
======================
module sm1(in8, latch8, latch8tag, clk, reset, out_clk, out_ldy,
out_ldy_tag,out16);
input [7:0] in8;
input latch8;
input latch8tag;
input clk;
input reset;
output out_clk;
output out_ldy;
output out_ldy_tag;
output [15:0] out16;

wire [7:0] in8;
wire reset;
wire latch8;
wire latch8tag;
wire temp_clk;
wire clk;
wire counter_clk;
wire out_clk;

reg [15:0] out16;
reg [7:0] ff1;
reg [7:0] ff2;

reg [2:0] result;
wire counter_rst;
reg r_counter_rst;
reg clk_en;
reg out_ldy;
reg out_ldy_tag;

assign temp_clk = (latch8 ^ ~latch8tag);

always @(negedge temp_clk or posedge reset)
begin
if (reset)
ff1 <= 0;
else
ff1 <= in8;
end

always @(posedge temp_clk or posedge reset)
begin
if (reset)
begin
ff2 <= 0;
r_counter_rst<=0;
clk_en<=1;
end
else
begin
ff2 <= in8;
r_counter_rst<=1;
clk_en<=0;
end
end

assign counter_clk = ~(clk | clk_en);
assign out_clk=counter_clk;
assign counter_rst=r_counter_rst;

always @(posedge counter_clk or posedge counter_rst)
begin
if (counter_rst)
begin
result = 0;
r_counter_rst=0;
end
else
if (counter_clk)
begin
result = result + 1;
if (result==1)
out16 = {ff1,ff2};
else
if (result==5)
begin
out_ldy=1;
out_ldy_tag=0;
end
else
if (result==6)
begin
out_ldy=0;
out_ldy_tag=1;
clk_en=1;
end
end
end
endmodule

Berty · May 25, 2005

The requirement are somewhat strange saying latch and posedge so I
assume the
posedge is the important and the latch is just a "nickname" as
usually a latch is base on level and not edge.

Also there are some un clarity as for special condition but I assume
any undefined condition other part of the code take care of them.

Also keep in mind that while you can play with logic to combine clock
edges unless you run out of resource this is usually unadvisable.

So here one example as for how you can do what you want :

Notice that synthesis can/should remove about half of the code however
for more clarity of reading I believe the below is easier to understand
rather than using the flags and glue logic that will get the same
result but be less clear.

`timescale 1ns/1ns

module latch_ex (
in8 ,
latch8 ,
latch8tag ,
latch16 ,
out16 ,
reset );

input [7:0] in8 ;
input latch8 ;
input latch8tag ;
input latch16 ;
output [15:0] out16 ;
input reset ;

reg [7:0] in8_latch8_pos ;
reg [7:0] in8_latch8tag_neg ;
reg flag1a ;
reg flag1b ;
wire flag1 = flag1a || flag1b ;
reg [7:0] in8_latch8tag_pos ;
reg [7:0] in8_latch8_neg ;
reg flag2a ;
reg flag2b ;
wire flag2 = flag2a || flag2b ;
reg flag3 ;
wire clr_flag1 = reset || flag3 ;
wire clr_flag2 = reset || flag1 ;
wire clr_flag3 = reset || flag2 ;
reg [15:0] out16 ;
always @ (posedge latch8 or posedge reset)
if (reset)
in8_latch8_pos <= #1 0 ;
else
in8_latch8_pos <= #1 in8 ;

always @ (negdege latch8tag or posedge reset)
if (reset)
in8_latch8tag_neg <= #1 0 ;
else
in8_latch8tag_neg <= #1 in8 ;

always @ (posdege latch8 or posedge clr_flag1)
if (clr_flag1)
flag1a <= #1 0 ;
else
flag1a <= #1 1 ;

always @ (negedge latch8tag or posedge clr_flag1)
if (clr_flag1)
flag1b <= #1 0 ;
else
flag1b <= #1 1 ;

always @ (negedge latch8 or posedge reset)
if (reset)
in8_latch8_neg <= #1 0 ;
else
in8_latch8_neg <= #1 in8 ;

always @ (posdege latch8tag or posedge reset)
if (reset)
in8_latch8tag_pos <= #1 0 ;
else
in8_latch8tag_pos <= #1 in8 ;

always @ (negedge latch8 or posedge clr_flag2)
if (clr_flag2)
flag2a <= #1 0 ;
else
flag2a <= #1 1 ;

always @ (posdege latch8tag or posedge clr_flag2)
if (clr_flag2)
flag2b <= #1 0 ;
else
flag2b <= #1 1 ;

always @ (posdege latch16 or posedge reset)
if (reset)
out16 <= #1 0 ;
else
casex({flag2b,flag2a,flag1b,flag1a})
4'b0101 : out16 <= #1 {in8_latch8_neg ,in8_latch8_pos };
4'b0110 : out16 <= #1 {in8_latch8_neg ,in8_latch8tag_neg};
4'b1001 : out16 <= #1 {in8_latch8tag_pos,in8_latch8_pos };
4'b1010 : out16 <= #1 {in8_latch8tag_pos,in8_latch8tag_neg};
default : out16 <= #1 16'hdead ; // Undefine conditions
endcase

always @ (posdege latch16 or posedge clr_flag3)
if (clr_flag3)
flag3 <= #1 0 ;
else
flag3 <= #1 1 ;

endmodule

Have Fun.

state machine without clock

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