State Machine with a for loop problem...

[Steven Menk]

I'm working on a state machine where I need to implement basically a
for-loop with in a state machine and have run into a problem.

I'm using Xilinx Foundation 7.1SP4, working in VHDL, targeting a
Virtex-II. I have it setup where I can ouput signals to a logic
analyzer to see what's going on.

Here's how I define my states:

type MAIN_STATE_TYPE is (M0, M1, M2, M3, M4, M4A, M4B, M5, M5A, M6, M7,
M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20);

signal MCS, MNS: MAIN_STATE_TYPE;

Here's my process to go from one state to the next:

process(clk_int2, status0)
begin
if status0 = '1' then
mcs <= M0;
elsif clk_int2 = '1' and clk_int2'event then
mcs <= mns;
end if;
end process;

Here' the process (edited for clarity) that handles the states:

process(mcs, sync(2), acw, counter)
begin
case mcs is
when M0 =>
if sync(0) = '1' then
cnt <= acw(19 downto 0);
counter <= "00000000000000000000";
mns <= M1;
else
mns <= M0;
end if;
when M1 => -- Do work until M9
when M9 =>
counter <= counter + "00000000000000000001";
when M10 =>
if counter = cnt then
mns <= M11;
else
mns <= M1;
end if;
when M11 => -- Output results mns <= M0
when others => mns <= M0;
end case;
end process;

"acw" is a 36 bit word that comes into the FPGA.

So basically what I want to do is sit and wait for the sync(2) signal
to tell my that my cnt which is the lowest 20 bits of acw is valid.
That part seems to work. The states M1 though M9 that I commented out
seem to work fine. Outputing data seems to work fine.

The problem seems to be the if counter = cnt statement. If I comment
that out and just go to M11 then back to M0 to wait for the next cnt
then it works fine. If I comment out the counter <=
"00000000000000000000" statement and the if statement and look at
counter, then it seems to work fine (it counts). I've also tried
different variations on it such as using a counter core, doing a two
state solution where I have a signal called "next_counter" and do
next_counter <= counter + x"00001"; and several other variations on
that. With the if statement in place counter never changes from
x"00000" and I never get out of the M1 to M9 loop.

What am I doing wrong?

 

[backhus]

Hi Steven,
besides some minor things like the incomplete sensitivity list and
sync(0) in the if instead of sync(2) as mentioned in your text
everything seems ok so far.

But...
Your counter will run from 0 to "1...1" (over and over again) if not
stopped by the compare in M10. Have you made sure in your simulation
that cnt has a valid value in the counter range? That is: No "X","U","Z"
etc. bits in it? Otherwise the compare will always fail, and you have
the behavior you observe.

Do you change cnt or counter in any way in M1..M9? I hope not.

Have a nice simulation

Eilert

 

[Steven Menk]

At this point I'm not simulating, but using a logic analyser on real
hardware. I'm getting some just generally odd behavior from the =, <,
and > operators. Weird stuff. I may go back to ModelSim to try to
figure out what's going on...

Thanks. I'll post some of my results here in a while.

 

[Andy Peters]

Steven Menk wrote:

At this point I'm not simulating, but using a logic analyser on real
hardware. I'm getting some just generally odd behavior from the =, <,
and > operators. Weird stuff. I may go back to ModelSim to try to
figure out what's going on...

That would be wise ...

-a

 

[jens]

Your counter isn't synchronous- that will cause a lot of strange things
to happen.

Simulation should also show strange results, and is a lot quicker and
easier than programming a part and using a logic analyzer.

 

[Steven Menk]

Good point about the synchronous counter. I re-did it so that my
process looks like this:
process(clk_int2, status0)
begin
if status0 = '1' then
mcs <= M0;
elsif clk_int2 = '1' and clk_int2'event then
mcs <= mns;
counter <= next_counter;
end if;
end process;

And added either a next_counter <= x"00000";, next_counter <= counter;
or next_counter <= counter + x"00001"; in each of my states. This
simulates correctly. I haven't had a chance to run it on the actual
hardware yet.

 

[backhus]

jens schrieb:

Your counter isn't synchronous- that will cause a lot of strange things
to happen.

Simulation should also show strange results, and is a lot quicker and
easier than programming a part and using a logic analyzer.

Hi Jens,

you are right, I missed that point.

In simulation: Each deltacycle the case process is triggered during M9
the counter increments infinite. May even crash the simulator due to a
combinational loop.

In hardware: The synthesis tool will generate an adder with feedback and
enable that runs wild when enabled.

That's why I use a 3 process model that separates branch conditions from
outputs and the output process is always clocked.

have a nice simulation
Eilert

 

[Steven Menk]

It did some pretty wacky stuff in the simulation alright.

Of course it doesn't seem much better now. It simulates (ModelSim Post
Place and Route) just fine with the changes I made above, but it
doesn't run in the actual hardware... I'll try to track down where I'm
getting stuck.

Thanks.

 

[Steven Menk]

Got it. Hardware thing. What goober design this thing? Oh wait...

Thanks for the help!