state machine interaction with a xilinx block ram

[alison]

Hello everyone,

I have a design which has a FSM acting as a controller for an
algorithm.
It has 25 states but three of them are used for:

state 5 --Reading data from the block ram by setting the en, rw,
address signals
and using a variable name data which is declared as 'reg' in the state
machine
to latch data out of the ram.

state 6-- add a constant value to 'reg data' and set set the dataout
equall to that eg dataout = data +5;
then set en, rw and address variables so that this value gets written
in ram.

state7- wait a clk cycle.

The variable are defined in the statemachine module as

reg [15,0] data; // its further defined as input
reg [15,0] address; // its further defined as output
reg [15,0] dataout; // its further defined as output


and so on

these variables are also assigned a value of zero in default state to
avoid latches

But only three states use them and rest do not.


PROBLEM functional simmulation is fine

Place and route tool is removing the ram saying that all the above
signals are sourceless. Although i can see them connected correctly
after synthesis.


Question; Why is data becomming a latch sive i have it assigned a
value both in
reset and default state and its being utilized in state 5 ,6 ,7.



Thanks for the help