State machine: how to stay in a state?

[David Lamb]

Hi,
When writing a vhdl state machine, is there an easy way to stay in a given
state for n clock cycles? I always end up having another process with a
counter, enable the counter in that particular state, and having a <if count
= n> statement in the state transition process. However, the counter needs
to be reset in the state before and it ends up being very confusing. Is it
possible to do this directly in the state machine process?

Thanks

Here is the type of state machine I usually use:

FSM_transitions: PROCESS (reset, clock) -- synchronous FSM
BEGIN
If reset = '1' THEN
state <= Rst;
ELSIF(clock'EVENT AND Clock = '1') THEN
CASE state IS
WHEN Rst =>
state <= Idle;
WHEN Finish =>
state <= Idle;
END CASE;
END IF;
END PROCESS;

FSM_OUTPUTS: PROCESS(state)
BEGIN
CASE state IS
WHEN Rst =>
count_reset <= '1';
WHEN Finish =>
Done <= '1';
END CASE;
END PROCESS;

 

[MM]

David,

Here is your code slightly modified:

FSM_transitions: PROCESS (reset, clock) -- synchronous FSM
variable count :integer;
BEGIN
If reset = '1' THEN
state <= Rst;
ELSIF(clock'EVENT AND Clock = '1') THEN
CASE state IS
WHEN Rst =>
count := IDLE_TIME;
state <= Idle;
WHEN Idle =>
count := count -1;
if count=0 then
state <= Finish;
count :=IDLE_TIME;
end if;
WHEN Finish =>
state <= Idle;
END CASE;
END IF;
END PROCESS;

Remember to watch where you reset the counter so it works correctly every
time.


/Mikhail



"David Lamb" <gretzteam_nospam@yahoo.com> wrote in message
news:bk4mdp$h5k$1@home.itg.ti.com...

Hi,
When writing a vhdl state machine, is there an easy way to stay in a given
state for n clock cycles? I always end up having another process with a
counter, enable the counter in that particular state, and having a <if
count
= n> statement in the state transition process. However, the counter needs
to be reset in the state before and it ends up being very confusing. Is it
possible to do this directly in the state machine process?

Thanks

Here is the type of state machine I usually use:

FSM_transitions: PROCESS (reset, clock) -- synchronous FSM
BEGIN
If reset = '1' THEN
state <= Rst;
ELSIF(clock'EVENT AND Clock = '1') THEN
CASE state IS
WHEN Rst =
state <= Idle;
WHEN Finish =
state <= Idle;
END CASE;
END IF;
END PROCESS;

FSM_OUTPUTS: PROCESS(state)
BEGIN
CASE state IS
WHEN Rst =
count_reset <= '1';
WHEN Finish =
Done <= '1';
END CASE;
END PROCESS;