state machine handshaking

[fpgawizz]

I have a state machine in a top level module. This top level module has a
component which is a state machine as well. All I am trying to do is
monitor the outputs of this component state machine. My top level state
machine provides some inputs to this component state machine and then
monitors and takes actions after looking at the component's FSM outputs. I
have a signal "X" mapped to the output port "Y" of my component FSM. When
i synthesize, I get a bunch of latches on Y, and X saying that Y is not
connected in my top level module.Yes they are indeed not connected, how do
I do what i am trying to do without those latches?

thanks

 

[Mike Treseler]

fpgawizz wrote:

I have a state machine in a top level module. This top level module has a
component which is a state machine as well. All I am trying to do is
monitor the outputs of this component state machine.

You can do this by writing a testbench
and running a simulation.

-- Mike Treseler

 

[fpgawizz]

I need this to work on hardware as well. My toplevel FSM provides a read
and write enable to my memory controller FSM (Which is a component) and
then I assign the outputs of the memory controller FSM to some signal in
my top level.

 

[Mike Treseler]

fpgawizz wrote:

I need this to work on hardware as well.

Write a testbench for your top design
entity -- whatever that is --
and run a simulation. Debugging
by trial and error synthesis might be
more difficult than learning simulation.

Consider a synchronous process
to eliminate latches.

Consider dissolving your wrapped
hierarchy into a single design entity
to simplify your design.


-- Mike Treseler