state machine description

[ALuPin@web.de]

Hi,

When checking some condition which is responsible for jumping
back to some known state within a state machine
I have done the following :

process(rst, clk)
begin
if rst='1' then
ls_state <= s_ini;

elsif rising_edge(clk) then

case ls_state is

...
when s_0 =>
...
if ls_condition='1' then
ls_state <= s_known;
end if;
when s_1 =>
...
if ls_condition='1' then
ls_state <= s_known;
end if;
when s_2 =>
...
if ls_condition='1' then
ls_state <= s_known;
end if;
...
end case;
end if;
end process;


Can the FSM be replaced with the following description ?

process(rst, clk)
begin
if rst='1' then
ls_state <= s_ini;

elsif rising_edge(clk) then

case ls_state is
...
when s_0 =>
...
when s_1 =>
...
when s_2 =>
...
end case;

if ls_condition='1' then
ls_state <= s_known;
end if;

end if;
end process;

Thank you for your comments.

Rgds
André

 

[Mike Treseler]

ALuPin@web.de wrote:

Can the FSM be replaced with the following description ?
....
end case;

if ls_condition='1' then
ls_state <= s_known;
end if;

Yes. Same logic, easier to read.

-- Mike Treseler

 

[KJ]

Another way to write it is what is listed below. In my opinion, it
more clearly represents what you're trying to express which is that if
'ls_condition = 1' then you want to go to a known state and there is no
point evaluating the case statement.

Either way will synthesize to exactly the same output so it becomes
somewhat of a style issue more than anything.

process(rst, clk)
begin
if rst='1' then
ls_state <= s_ini;


elsif rising_edge(clk) then

if ls_condition='1' then
ls_state <= s_known;
else
case ls_state is
...
when s_0 =>
...
when s_1 =>
...
when s_2 =>
...
end case;
end if;
end if;
end process;

 

[ALuPin@web.de]

Hi Mike, KJ,

thank you for your comments.

Rgds
André