state machine coding

[mysticlol]

Is this way of state machine coding is correct?

process(reset, clk100)
Begin
if reset='1' then
present_state <= idle;
elsif rising_edge(clk100) then
present_state <= next_state;
end if;
end process;

process(reset, clk100)
begin
if reset='1' then
clk_cnt <= (others => '0')
elsif rising_edge(clk100) then
clk_cnt <= clk_cnt + '1';
end if;
end process;

process(present_state, clk_cnt)
begin
case present_state is
when idle => next_state <= present_state;
when shiftout => if conv_integer(clk_cnt) <= 15 then next_state <=
shiftin; else next_state <= shiftout; end if;
when shiftin => if conv_integer(clk_cnt) <= 31 then next_state <=
shiftin; else next_state <= idle; end if;
when others => next_state <= idle;
end case;
end process;

process(reset, clk100)
begin
if reset='1' then
Idle_out <= '0'; shiftout_out <= '0'; shiftin_out <= '0';
elsif rising_edge(clk100) then
case present_state is
when idle => Idle_out <= '1; shiftout_out <= '0'; shiftin_out
<= '0';
when shiftout => Idle_out <= '0'; shiftout_out <= '1;
shiftin_out <= '0'; data(31 downto 0) <= sig_out & data(31 downto
1);
when shiftin => Idle_out <= '0'; shiftout_out <= '0';
shiftin_out <= '1; data(31 downto 0) <= data(30 downto 0) & sig_in;
when others => Idle_out <= '1; shiftout_out <= '0'; shiftin_out
<= '0';
end case;
end if;
end process;


or is there a better way ? I dont want to use variables in my state
machine coding.
I feel using variables in RTL coding is an inefficient way of coding -
testbenches are exemption.

Please suggest.

Regards,
Krishna

 

[Mike Treseler]

mysticlol wrote:

Is this way of state machine coding is correct?
or is there a better way ?

This style question has many answers
and it has no answer.
Here are 50 recent postings on the subject:
http://tinyurl.com/hsrc7

I dont want to use variables in my state
machine coding.
I feel using variables in RTL coding is an inefficient way of coding -
testbenches are exemption.

In that case, I have nothing to add.

-- Mike Treseler

 

[mysticlol]

Hi Mike,
Thanx for the link.

Regards,
Krishna

Mike Treseler wrote:

mysticlol wrote:
Is this way of state machine coding is correct?
or is there a better way ?

This style question has many answers
and it has no answer.
Here are 50 recent postings on the subject:
http://tinyurl.com/hsrc7

I dont want to use variables in my state
machine coding.
I feel using variables in RTL coding is an inefficient way of coding -
testbenches are exemption.

In that case, I have nothing to add.

-- Mike Treseler

 

[Andy]

mysticlol wrote:

Is this way of state machine coding is correct?
....
or is there a better way ? I dont want to use variables in my state
machine coding.
I feel using variables in RTL coding is an inefficient way of coding -
testbenches are exemption.

Please suggest.

Regards,
Krishna

My opinion is that using variables in a single, clocked process is a
better, more efficient way to code state machines and their outputs.

Andy