State machine behavior question

Hey everyone,

I'm unsure about how a verilog state machine should behave if the
next_stage block is triggered by a signal on the rising edge of the
clock. What's happening my state machine is that the current_state and
next_state are changing at the exact same time and i'm not sure if
that is correct behavior?

initial begin
I_write = 0;
RESET = 0;
# 90 RESET = 1;
# 15 RESET = 0;
# 82.5 I_write = 1;
# 15 I_write = 0;
end

always@(I_write or time_update or current_state) // combinatorial
block
begin
case(current_state)
IDLE:begin
if(I_write)
begin
$display($time, "print1 %b %b %b", RESET, current_state,
next_state);
next_state = WR_DATA;
end
else if(time_update)
begin
$display($time, "print2 %b %b %b", RESET, current_state,
next_state);
next_state = WR_TIME;
end
else
begin
$display($time, "print3 %b %b %b", RESET, current_state,
next_state);
next_state = IDLE;
end
end
WR_TIME:begin
if(time_update) begin
$display($time, "print4 %b %b %b", RESET, current_state,
next_state);
next_state = IDLE;
end
end
WR_DATA:begin
if(I_write)
begin
$display($time, "print5 %b %b %b", RESET, current_state,
next_state);
next_state = WR_DATA;
end
else
begin
$display($time, "print6 %b %b %b", RESET, current_state,
next_state);
next_state = IDLE;
end
end
endcase
end

always@(posedge clk or posedge RESET) //sequential block
begin
if(RESET)
begin
$display($time, "print7 %b %b %b", RESET, current_state,
next_state);
current_state <= IDLE;
end
else
begin
$display($time, "print8 %b %b %b", RESET, current_state,
next_state);
current_state <= next_state;
end
end


This gives the following output:

.......
# 188print1 0 000 000
# 188print8 0 000 010
# 188print5 0 010 010
# 203print6 0 010 010
# 203print8 0 010 000
# 203print3 0 000 000
# 218print8 0 000 000
# 233print8 0 000 000
# 248print8 0 000 000
# 263print8 0 000 000
# 278print8 0 000 000
......

where at time 203 the current_stage and next_stage change at exactly
the same time.

I'm unsure if this is correct behavior as i think the current_stage
should change on the next rising clk edge after the next_stage changes
and not at the same time - is that correct?

Am i missing something from my state machine?

Any help would be appreciated.

Cheers,


Rob.

 

[John_H]

robquig...@gmail.com wrote:

Hey everyone,

I'm unsure about how a verilog state machine should behave if the
next_stage block is triggered by a signal on the rising edge of the
clock. What's happening my state machine is that the current_state and
next_state are changing at the exact same time and i'm not sure if
that is correct behavior?

snip
.....

where at time 203 the current_stage and next_stage change at exactly
the same time.
snip

The "same time" is probably misleading. Are you familiar with how
simulators behave with respect to scheduling events based on changes
in clock and signal levels?

You probably have your registered state changing in the scheduled time
slot after the clock changes polarity. When that registered value
changes, the combinatorial value you want to generate sees a change in
the sensitivity list so the next scheduling timeslot changes the
combinatorial version.

If you increase the resolution of your time display, decrease the
resolution of your `timescale, or add #1 style delays in your
next_state assignments, you may find the changes aren't "the same
time" but ever so slightly different as one would expect when a signal
with no delay propagates through logic.

This is pretty basic simulation background and should only be a
surprise to the newly indoctrinated. So... welcome!

- John_H

 

[glen herrmannsfeldt]

robquigley@gmail.com wrote:

I'm unsure about how a verilog state machine should behave if the
next_stage block is triggered by a signal on the rising edge of the
clock. What's happening my state machine is that the current_state and
next_state are changing at the exact same time and i'm not sure if
that is correct behavior?

If you have zero hold time registers, then that is fine.

In real logic they usually won't change quite that fast,
but it is allowed in most modern logic families.

-- glen

 

[Jonathan Bromley]

On Thu, 19 Jun 2008 10:30:24 -0700 (PDT), robquigley@gmail.com wrote:

I'm unsure about how a verilog state machine should behave if the
next_stage block is triggered by a signal on the rising edge of the
clock. What's happening my state machine is that the current_state and
next_state are changing at the exact same time and i'm not sure if
that is correct behavior?

It looks about right to me, but perhaps I can suggest
the following bit of diagnostics.

(1) Track the behaviour of each and every signal in
a waveform viewer, or like this:

always @(posedge clock)
$display("clock rise @t=%0d", $time);
always @(current_state)
$display("current_state changed to 'b%b @t=%0d",
current_state, $time);
...
and so on for all the important signals, including inputs.

(2) Having seen that, try adding a delay in the register
updates, modeling clock-to-output delay:

always @(posedge clk or posedge RESET)
if(RESET)
current_state <= IDLE;
else
current_state <= #1 next_state;

(no need for all those print statements now that
you're monitoring the signal changes in separate
always blocks)

This, along with inspection of waveforms, should help
you to get a feel for what's going on. There's not
much wrong with your code that I can see, apart from
my distaste for explicit next-state signals (which
has already been chewed over here ad nauseam) and
your use of tabs instead of spaces (eugh!).

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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