State definition and display: literal vs. symbolic in ModelS

[Paul Urbanus]

I have a design with a state machine whose present state is also an
output at the top level. At the top level (corresponding to I/O pins),
this state signal is an slv. The values for the various states are also
defined in the FPGA application interface spec.

I have explicitly defined the various states as constants, but when I
look at 'dips_ctrl_state' in ModelSim's waveform viewer, I can't get it
to use the symbolic names I've assigned when I set the radix to
'symbolic'. For instance, I would like to see 'CS_RESET' instead of '0'.

Here's the code I have to define the various states and propagate the
state to the top level.

======== from the entity port declarations ==========
disp_ctrl_state : out std_logic_vector(2 downto 0);

======== from the architecture declarations ========
--
-- Display Control State (to reformatter)
--
signal i_disp_ctrl_state : std_logic_vector(2 downto 0);
constant CS_RESET : std_logic_vector(2 downto 0) := "000";
constant CS_IDLE : std_logic_vector(2 downto 0) := "001";
constant CS_LOAD_DMD : std_logic_vector(2 downto 0) := "010";
constant CS_RDY_EXP : std_logic_vector(2 downto 0) := "011";
constant CS_EXPOSING : std_logic_vector(2 downto 0) := "100";
constant CS_RDY_CLR : std_logic_vector(2 downto 0) := "101";
constant CS_PARKED : std_logic_vector(2 downto 0) := "110";
constant CS_RESVD : std_logic_vector(2 downto 0) := "111";

======== from the architecture code ========
disp_ctrl_state <= i_disp_ctrl_state;


If I try and assign the states be defining a unique state type and
enumerating the states, then I can't get the explicit state values I
need to meet the interface spec. And I get an (expected) type mismatch
when I try and assign the state type to the std_logic_vector at the top
level. However, the symbolic waveform display works great.

======== from the entity port declarations ==========
disp_ctrl_state : out std_logic_vector(2 downto 0);

======== from the architecture declarations ========
--
-- Display Control State (to reformatter)
--
-- type i_disp_ctrl_state_type is (
-- CS_RESET,
-- CS_IDLE,
-- CS_LOAD_DMD,
-- CS_RDY_EXP,
-- CS_EXPOSING,
-- CS_RDY_CLR,
-- CS_PARKED,
-- CS_RESVD );
-- signal i_disp_ctrl_state : i_disp_ctrl_state_type;

======== from the architecture code ========
disp_ctrl_state <= i_disp_ctrl_state;


QUESTION: Is there a way to get ModelSim to show my std_logic_vector
state values symbolically?

QUESTION: If not, is there a way I can assign literal values to the
state types so I can view them symbolically in ModelSim? Can I cast them
to std_logic_vector before assigning them to the top-level I/O pins, so
I can at least view the internal state symbolically?

TIA
Urb

 

[Paul Urbanus]

Mike Treseler wrote:

See page 26 of
http://www.hep.wisc.edu/~gowrisha/Tutorial.pdf

--- Mike Treseler

Mike,

Thanks for the pointer, but a newbie tutorial on ModelSim isn't what I
need. If you re-read my post, you'll see that I'm asking a deeper
question, the answer which is not "select the 'symbolic' radix for the
signal(s) in question, as indicated in the tutorial".

What I'm asking is how to get a symbolic display of a state if the
signal is a std_logic_vector and the states are defined as constants.

Or, how to assign explicit slv values to an enumerated type such as a
state type.

I know that I can brute force this and add a case statement to my code
that will allow me to convert the enumerated state type to an slv, which
I can than pass to the top level I/O pins. Then, I can view state
symbolically by just displaying the enumerated state signal from inside
the design. However, I was looking for a more elegant solution, which
may not exist.

Urb