state change

[Urban Stadler]

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

thanks
urban

 

[Urban Stadler]

thanks for the answer but is there a better solution?
my signals are not syncron to the clock.
i need something that works 100% without glitches.

i tried the "transition" but that gives me an error?
is that not synthesizeable?

 

[Ken Smith]

In article <sh8Zc.174947$sh.142454@fed1read06>,
Urban Stadler <u.stadler@pfeilheim.sth.ac.at> wrote:

hi

how do i detect a state change of a signal in vhdl.
i want to detect if a signal changes from high to low or reverse.
is there a way so i can reset a counter for example?
but i only want to reset it when the change occures.

If you want it to be psudo-edge operated:

Lets say your input signal is called ResetOnRise.

In the process section that makes the counter count, you assign another
signal like this:

DelayedResetOnRise <= ResetOnRise;

Now if you combine them like this:

(ResetOnRise AND NOT DelayedResetOnRise)

you have the needed combination to zero the counter.

WARN:

You can creat timing glitches if ResetOnRise is not timed to same clock as
the DelayedResetOnRise. If thats the case you need a tad more logic to
get the job done.


--
--
kensmith@rahul.net forging knowledge