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Ranjith

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Can anyone suggest me some small project which can get me started on to this VHDL.

Regards,
ranair123
 
Ranjith wrote:
Can anyone suggest me some small project which can get me started on to this VHDL.
1. Find a vhdl testbench example like this:
http://groups.google.com/groups?q=oe_demo+yang

2. Get a simulator and learn how to compile and
load the testbench without errors.

3. Add functions to the model and to the test.

4. Read your VHDL book and repeat from 1 until
you know how to use the language for synth and sim.

-- Mike Treseler
 
Aldec has a downloadable interacive tutorial. It is perfect, all aspects are
described in very comprihensive and compact form. You can download a 20-day
evaluation version of their VHDL development IDE called ActiveHDL. It has
much better support of VHDL and saves lots of nerves.
 
http://www.aldec.com/FreeTutorials/EvitaVerilog.exe (4.3MB)


Valentin Tihomirov wrote:

Aldec has a downloadable interacive tutorial. It is perfect, all aspects are
described in very comprihensive and compact form. You can download a 20-day
evaluation version of their VHDL development IDE called ActiveHDL. It has
much better support of VHDL and saves lots of nerves.
 

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