Guest
Hi all,
I am implementing some logic in FPGA(Transmit/Reveive).
On the receive data first i look for a 8- bit pattern to detect the
START pattern.Now my question is in the data also i may get the same
START pattern how to distinguish between the START /STOP pattern and
data.
Any comments are appreciated.
Regards,
Prav
I am implementing some logic in FPGA(Transmit/Reveive).
On the receive data first i look for a 8- bit pattern to detect the
START pattern.Now my question is in the data also i may get the same
START pattern how to distinguish between the START /STOP pattern and
data.
Any comments are appreciated.
Regards,
Prav