standard symbol size?

[Erik Wanta]

I there an industry standard symbol size for Cadence symbols (res,
ind, nmos, pmos,standard cells, ...)? Where is the standard defined?
---
Erik

 

[John Gianni]

erikwanta@starband.net (Erik Wanta) wrote in message news:<84018314.0402152145.fcea6e1@posting.google.com>...

I there an industry standard symbol size for Cadence symbols (res,
ind, nmos, pmos,standard cells, ...)? Where is the standard defined?

Hi Erik,

I do not know if there is an 'official' standard; maybe the guys at
the "Silicon Integration Initiative" ( http://www.si2.org ) or at
the "VSI Alliance" ( http://www.vsii.org ) have an industry standard
symbol shape, pinout, and size defined for devices and std cells.

There certainly is an ad-hoc Cadence standard symbol size for these.
That is, just about all (if not all) the CDK's from Cadence contain a
PDK and a standard-cell library which use well-known well-accepted
industry standard symbol sizes and shapes.

For example, all the PDK symbols (as far as I know) for the main
devices (nmos, pmos, diode, inductor, resistor, bjt, etc.) are of
the same size, shape, and pinout. The reason I know is my CIC Flow
Engineering Team takes our designs through the 180 and 90nm GPDK,
CSM 180nm PDK, UMC 180nm PDK, TSMC 180nm MS & 130 nm FSG, etc.

The CIC Flow team runs a schematic re-referencer each time which swaps
out symbols (and runs mathematical equations on properties as needed).
Then we simulate & optimize using Spectre & Aptivia; and we quickly
lay the chips out using a combination of Virtuoso XL, NeoCell, etc.
and verify with Assura (on Linux & Solaris) in CDBA & on OpenAccess.

Motorola has similar functionality, I am told, written by our Services
guys, for re-referencing schematics. Rarely, if ever, do we see an open
wire in the re-referencing process.

For example, the Cadence Hummingbird PLL (which Motorola & National
helped verify in the Cadence generic 180nm & generic 90nm process)
has been ported to all the processes above, and more - all the while,
the symbols have never needed to be manually re-wired.

In addition, each of the Cadence CDKs contain plenty of standard-cell
symbol shapes (some directly from existing Cadence libraries) which can
be considered 'industry standard'. My team is building the latest CDK
which we hope, when it's released, becomes the de-facto generic standard
for Cadence Custom IC designers. Others built the earlier CDK using
standard standard-cell symbols.

In fact, we designed & built Eaglet (a 2.4 Ghz password-protected digital
switch) expressly for the purpose of providing a baseline set of components
and a baseline flow for all the Cadence tools (scores of 'em) both custom
and digital, including system functional on the TSMC 180nm and the Cadence
180nm CDK, in OpenAccess and in CDBA.

Our 180nm Cadence CDK has already been released (on OpenAccess & CDBA)
and is available to university programs (along with the complete Eagle RF,
Analog, Mixed-Signal, Digital, Memory, I/O, test chip containing a 2.4
Ghz LNA & Mixer, an analog 3 Mhz Opamp & Filter, a mixed-signal 1 Ghz
PLL & 200Mhz 5-bit flash ADC, a 16-bit digital FFT & DMA, with syncronous
dual-port RAM & ROM, with I/O cells & bond pads, etc.) all available
for download today on http://crete.cadence.com (for university classes).

John Gianni
ALL my USENET posts are PERSONAL opinion; no mail is read from this address!