B
BigD
Guest
Hi fellow members,
I have made a very simple RISC, and it has worked successfully giving
the right values in the registers. My tradition is to always say wat
ive done before saying what I need help with. basically, i have
achieved system objectives by reordering machine instructions - i am
now looking to implement a hardware resolution to the data hazards i.e.
pipeline stalling. its a simple 'one stage' pipeline. I have tried to
use a multiplexer but maybe i am not doing it right. How can I stall a
pipeline in VHDL if a value is written to a register and an attempt is
made to read it on the next cycle(data hazard).
I have made a very simple RISC, and it has worked successfully giving
the right values in the registers. My tradition is to always say wat
ive done before saying what I need help with. basically, i have
achieved system objectives by reordering machine instructions - i am
now looking to implement a hardware resolution to the data hazards i.e.
pipeline stalling. its a simple 'one stage' pipeline. I have tried to
use a multiplexer but maybe i am not doing it right. How can I stall a
pipeline in VHDL if a value is written to a register and an attempt is
made to read it on the next cycle(data hazard).