Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Is there a canonical topology to stack them in series
such that one gets a switch with a higher Vds rating
but maintain approximately the same switching speed?
Figure 9.111, pg.697On Friday, March 6, 2020 at 3:48:43 PM UTC-5, John Larkin wrote:
On Fri, 6 Mar 2020 14:24:28 -0500, bitrex <user@example.net> wrote:
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Win is right, but you might also consider silicon carbide fets. How
much total voltage do you need? Can the switch sink to ground? How
fast? How often?
Sometimes one can arrange to drive only the lower, grounded-source fet
in a string.
I vaguely remember a circuit in AoE3 like that... with resistors and /or
zeners to turn on the other gates? But not as fast I'd guess.
George H.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
I vaguely remember a circuit in AoE3 like that... with resistors and /orOn Fri, 6 Mar 2020 14:24:28 -0500, bitrex <user@example.net> wrote:
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Win is right, but you might also consider silicon carbide fets. How
much total voltage do you need? Can the switch sink to ground? How
fast? How often?
Sometimes one can arrange to drive only the lower, grounded-source fet
in a string.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
On Fri, 6 Mar 2020 14:24:28 -0500, bitrex <user@example.net> wrote:
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Win is right, but you might also consider silicon carbide fets. How
much total voltage do you need? Can the switch sink to ground? How
fast? How often?
Sometimes one can arrange to drive only the lower, grounded-source fet
in a string.
On Friday, March 6, 2020 at 4:16:50 PM UTC-5, George Herold wrote:
On Friday, March 6, 2020 at 3:48:43 PM UTC-5, John Larkin wrote:
On Fri, 6 Mar 2020 14:24:28 -0500, bitrex <user@example.net> wrote:
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Win is right, but you might also consider silicon carbide fets. How
much total voltage do you need? Can the switch sink to ground? How
fast? How often?
Sometimes one can arrange to drive only the lower, grounded-source fet
in a string.
I vaguely remember a circuit in AoE3 like that... with resistors and /or
zeners to turn on the other gates? But not as fast I'd guess.
George H.
Figure 9.111, pg.697
... I only got 50-volts in stock ...
I was mostly hoping for an expedient, temporary solution
as I need to test a circuit that requires 100 volt-rated
FETs but I only got 50-volts in stock ...
bitrex wrote...
I was mostly hoping for an expedient, temporary solution
as I need to test a circuit that requires 100 volt-rated
FETs but I only got 50-volts in stock ...
Isolated high-voltage drivers require special circuits,
usually involving transformer-powered circuit fragments.
But at voltages below 600V, you can use high-side driver
ICs, like Fig 3x.108, Table 3x.5. Drive sets of stacked
MOSFETs. Probably none of those in stock either, huh?
I was mostly hoping for an expedient, temporary solution
as I need to test a circuit that requires 100 volt-rated
FETs but I only got 50-volts in stock ...
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
I was mostly hoping for an expedient, temporary solution
as I need to test a circuit that requires 100 volt-rated
FETs but I only got 50-volts in stock ...
Try two series FETs, with the high-side FET shorted gate-source.
Then drive the low-side FET. The high-side will avalanche when
it sees the full 100V. Will this work? I doubt it. But at a
glance I can't see why not...
https://pdfslide.net/documents/nanosecond-square-high-voltage-pulse-generator-for-electro-optic-switch.html
Is there a canonical topology to stack them in series such that one gets
a switch with a higher Vds rating but maintain approximately the same
switching speed?
plastcontrol.ru@gmail.com wrote...
https://pdfslide.net/documents/nanosecond-square-high-voltage-pulse-generator-for-electro-optic-switch.html
That circuit looks good. Nice find!
The secret is the gate capacitors to GND, with zener
protection diodes for the FETs Vgs. If there's no load
for pullup, a high-side switch will also be required.
But it's not clear why the high-side switch can't use
the same trick as the low side, employing only one
isolated gate drive on the bottom FET of the stack.
--
Thanks,
- Win
On Saturday, March 7, 2020, Winfield Hill wrote:
plastcontrol.ru@gmail.com wrote...
https://pdfslide.net/documents/nanosecond-square-high-voltage-pulse-generator-for-electro-optic-switch.html
That circuit looks good. Nice find!
Look at AoE3 figure 9.111, Maybe Paul put this one in there?
The secret is the gate capacitors to GND, with zener
protection diodes for the FETs Vgs. If there's no load
for pullup, a high-side switch will also be required.
But it's not clear why the high-side switch can't use
the same trick as the low side, employing only one
isolated gate drive on the bottom FET of the stack.