STA Problem on Asynchronous FIFO

[vcar]

The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock
A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now
the problem comes when performing STA. The Timing Analyzer reports
that:

Slack: -10.394ns (requirement - (data path - clock path skew +
uncertainty))
Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC
(RAM)
Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23
(FF)
Requirement: 0.250ns
Data Path Delay: 2.008ns (Levels of Logic = 0)
Clock Path Skew: -8.259ns (3.005 - 11.264)
Source Clock: trn_clk_c rising at 56.000ns
Destination Clock: DDR2_CLK0 rising at 56.250ns

For certain path crossing the different clock domains, the auto
constraints turned out to be 0.25ns (4ns – 3.75ns). This is impossible
to achieve.

What should I do to pass the STA?

 

[Muzaffer Kal]

On Sun, 28 Jun 2009 03:21:50 -0700 (PDT), vcar <hitsx@163.com> wrote:

The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
...
What should I do to pass the STA?

You need to put a "false path" constraint between the two clocks of
the async fifo or any two unrelated clocks so that STA will ignore
them. Then of course you'll have to implement safe cross-clock-domain
techniques to implement any communication between them. Asynchronous
FIFOs are one solution.
---
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

 

[vcar]

On 6ÔÂ29ČŐ, ÉĎÎç1Ęą40ˇÖ, Muzaffer Kal <k...@dspia.com> wrote:

On Sun, 28 Jun 2009 03:21:50 -0700 (PDT), vcar <hi...@163.com> wrote:
The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
...
What should I do to pass the STA?

You need to put a "false path" constraint between the two clocks of
the async fifo or any two unrelated clocks so that STA will ignore
them. Then of course you'll have to implement safe cross-clock-domain
techniques to implement any communication between them. Asynchronous
FIFOs are one solution.
---
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Serviceshttp://www.dspia.com

All the communication between the two clock domains is through the
async FIFO. No other signals are crossing the two clock domains. So I
can safely add the false path, right?
What would the false path constraints be like? Is there an example?