SRL16 as synchronizer

H

Hans-Juergen Dorn

Guest
Hello All,

I'm wondering, if it's possible to use SRL16s to synchronize
external signals to your clock.

If I do the standard thing in VHDL, e.g. a couple of assignments in
a clocked process, then XST gives me a SRL anyway.

Mabe I could just leave it that way, without having to
instantiate FDEs manually?

Is there any difference w.r.t metastability in using SRLs
compared to FDs?

Regards Hans Dorn
 
Hi Hans-Juergen,
Try a search on Google groups "metastability srl". Top answer is a
discussion we had here called "Should I worry about metastability". Xilinx's
expert, Peter Alfke, said :-

I will not guarantee that SRL16s recover as fast from metastability as
the "normal" flip-flops that I documented, since SRLs are implemented in
a different circuit design. (Different might mean better or worse).

Ray Andraka replied:-

Actually, the SRL's are probably no good for that. They have a considerably
longer minimum pulse width than the regular flip-flops. I'm not privy to
the
actual construction, but I'd be it is more akin to latches than to real
flip-flops. Your best resynchronizer will use the regular flip-flops,
floorplanned to use adjacent slices within a CLB and using the fast direct
connect route between the flip-flops.

Which makes a lot of sense to me, the question is whether the latch type
construction of the SRL FFs is compensated for by the short routing delay
between the latch elements, they're in the same LUT structure, after all. My
guess is not, so until someone can be bothered to do the experiment, I'm
gonna stick with the regular FFs as Peter has tested this to death and so we
have hard data to work with. I don't suppose you'd like to do the
experiments??
So, rereading your post, it IS possible to use the SRLs to do the
resync, how well it works w.r.t metastability see above! Post some
frequencies, and you may get a better answer.
cheers, Syms.

"Hans-Juergen Dorn" <hjdorn@freenet.de> wrote in message
news:1lugrv0l01tsje6qbbvtnepoa9q7he4u6e@4ax.com...
Hello All,

I'm wondering, if it's possible to use SRL16s to synchronize
external signals to your clock.

If I do the standard thing in VHDL, e.g. a couple of assignments in
a clocked process, then XST gives me a SRL anyway.

Mabe I could just leave it that way, without having to
instantiate FDEs manually?

Is there any difference w.r.t metastability in using SRLs
compared to FDs?

Regards Hans Dorn
Click to expand...
 
Hans-Juergen Dorn wrote:

I'm wondering, if it's possible to use SRL16s to synchronize
external signals to your clock.
Click to expand...
If not having a reset is ok, then yes.

If I do the standard thing in VHDL, e.g. a couple of assignments in
a clocked process, then XST gives me a SRL anyway.
Click to expand...
That's what I would expect.

Mabe I could just leave it that way, without having to
instantiate FDEs manually?
Click to expand...
That's an excellent idea.
Easier to sim and more portable.

Is there any difference w.r.t metastability in using SRLs
compared to FDs?
Click to expand...
Don't know. Check the data sheet.

Or check fmax, with and without a reset.





-- Mike Treseler
 
I concur. The SRL16 structure is different from a conventional
flip-flop. Although it is only the Master latch in a flip-flop that is
reponsible for metastability (the Slave just does the read-out), this
might imply that there is no difference. But I still would be leary to
venture into untested territory. Also, if you use the SRL16 for more
than one bit of depth, you pick up latency.
I prefer erring on the side of solid conservatism.
(Technically, not politically).
It's too late for my hair color, but it's nice to be able to sleep at
night. :)
Peter Alfke
===========================
Symon wrote:
Hi Hans-Juergen,
Try a search on Google groups "metastability srl". Top answer is a
discussion we had here called "Should I worry about metastability". Xilinx's
expert, Peter Alfke, said :-

I will not guarantee that SRL16s recover as fast from metastability as
the "normal" flip-flops that I documented, since SRLs are implemented in
a different circuit design. (Different might mean better or worse).

Ray Andraka replied:-

Actually, the SRL's are probably no good for that. They have a considerably
longer minimum pulse width than the regular flip-flops. I'm not privy to
the
actual construction, but I'd be it is more akin to latches than to real
flip-flops. Your best resynchronizer will use the regular flip-flops,
floorplanned to use adjacent slices within a CLB and using the fast direct
connect route between the flip-flops.

Which makes a lot of sense to me, the question is whether the latch type
construction of the SRL FFs is compensated for by the short routing delay
between the latch elements, they're in the same LUT structure, after all. My
guess is not, so until someone can be bothered to do the experiment, I'm
gonna stick with the regular FFs as Peter has tested this to death and so we
have hard data to work with. I don't suppose you'd like to do the
experiments??
So, rereading your post, it IS possible to use the SRLs to do the
resync, how well it works w.r.t metastability see above! Post some
frequencies, and you may get a better answer.
cheers, Syms.

"Hans-Juergen Dorn" <hjdorn@freenet.de> wrote in message
news:1lugrv0l01tsje6qbbvtnepoa9q7he4u6e@4ax.com...
Hello All,

I'm wondering, if it's possible to use SRL16s to synchronize
external signals to your clock.

If I do the standard thing in VHDL, e.g. a couple of assignments in
a clocked process, then XST gives me a SRL anyway.

Mabe I could just leave it that way, without having to
instantiate FDEs manually?

Is there any difference w.r.t metastability in using SRLs
compared to FDs?

Regards Hans Dorn
Click to expand...
 
You might find a comment elsewhere in your timing report that fmax is
limited by the SRL minimum pulse widths, Twph + Twpl. The 150E-7 timing I
had up on my screen (SpeedPrint, v6.1i timing) shows Twph of 2100 ps; Twpl
isn't specified in the SpeedPrint output but I recall it's the same as Twph
resulting in an SRL-limited fmax of 238 MHz with no jitter and 50.00% duty
cycle.

You might be able to get XST to avoid inferring s1 as part of the SRL by
specifying to XST that it's an IOB register, allowing s2 and Q to be an SRL
if XST so chooses.

If Q was to be your "stable" value and s1 and s2 were metastability
registers, why not use s2 as the stable, synchronized value? I thought only
two registers were needed for proper metastability protection, the output of
s1 being a "maybe" that settles to a high or low by the time s2 grabs the
value.


"Hans-Juergen Dorn" <hjdorn@freenet.de> wrote in message
news:v1oirvs09jf6jaco5c7pt0luvoel60it5i@4ax.com...
On Mon, 17 Nov 2003 10:11:24 -0800, Peter Alfke <peter@xilinx.com
wrote:

I concur. The SRL16 structure is different from a conventional
flip-flop. Although it is only the Master latch in a flip-flop that is
reponsible for metastability (the Slave just does the read-out), this
might imply that there is no difference. But I still would be leary to
venture into untested territory.


Hi Hans-Juergen,
Try a search on Google groups "metastability srl". Top answer is a
discussion we had here called "Should I worry about metastability".
Xilinx's
expert, Peter Alfke, said :-

I will not guarantee that SRL16s recover as fast from metastability as
the "normal" flip-flops that I documented, since SRLs are implemented
in
a different circuit design. (Different might mean better or worse).

Mike Tresseler wrote
Is there any difference w.r.t metastability in using SRLs
compared to FDs?

Don't know. Check the data sheet.

Or check fmax, with and without a reset.

Hey, thank you all for answering!

The fmax of a single SRL seems to be way beyond the
capacity of the global clock nets. (At least for Spartan2E, that is)

If I do something like -

p : process(clk) is
signal s1, s2 : std_logic;
begin
if clk'event and clk='1' then
s1 <= A;
s2 <= s1;
Q <= s2;
end if
end process;

- I'll get an Fmax of 561Mhz on a XC2S50e-7 !!!
At least WP4.2's timing analyzer seems to think so...

But anyway, I guess I'll stick to throwing FDE's at all that
nasty stuff coming from the outside...

Regards Hans

P.S:

If you think, you found an easy way of doing something in VHDL,
you're probably doing it wrong. :eek:)
Click to expand...
 
One way to assure that XST will use regular FFs, not SRLs, is to
supply a Reset signal. SRLs do not have reset, so XST will avoid them.

"John_H" <johnhandwork@mail.com> wrote:

:You might find a comment elsewhere in your timing report that fmax is
:limited by the SRL minimum pulse widths, Twph + Twpl. The 150E-7 timing I
:had up on my screen (SpeedPrint, v6.1i timing) shows Twph of 2100 ps; Twpl
:isn't specified in the SpeedPrint output but I recall it's the same as Twph
:resulting in an SRL-limited fmax of 238 MHz with no jitter and 50.00% duty
:cycle.
:
:You might be able to get XST to avoid inferring s1 as part of the SRL by
:specifying to XST that it's an IOB register, allowing s2 and Q to be an SRL
:if XST so chooses.
:
:If Q was to be your "stable" value and s1 and s2 were metastability
:registers, why not use s2 as the stable, synchronized value? I thought only
:two registers were needed for proper metastability protection, the output of
:s1 being a "maybe" that settles to a high or low by the time s2 grabs the
:value.
:
:
:"Hans-Juergen Dorn" <hjdorn@freenet.de> wrote in message
:news:v1oirvs09jf6jaco5c7pt0luvoel60it5i@4ax.com...
:> On Mon, 17 Nov 2003 10:11:24 -0800, Peter Alfke <peter@xilinx.com>
:> wrote:
:>
:> >I concur. The SRL16 structure is different from a conventional
:> >flip-flop. Although it is only the Master latch in a flip-flop that is
:> >reponsible for metastability (the Slave just does the read-out), this
:> >might imply that there is no difference. But I still would be leary to
:> >venture into untested territory.
:>
:>
:> >> Hi Hans-Juergen,
:> >> Try a search on Google groups "metastability srl". Top answer is a
:> >> discussion we had here called "Should I worry about metastability".
:Xilinx's
:> >> expert, Peter Alfke, said :-
:> >>
:> >> I will not guarantee that SRL16s recover as fast from metastability as
:> >> the "normal" flip-flops that I documented, since SRLs are implemented
:in
:> >> a different circuit design. (Different might mean better or worse).
:>
:> Mike Tresseler wrote
:> >> Is there any difference w.r.t metastability in using SRLs
:> >> compared to FDs?
:>
:> >Don't know. Check the data sheet.
:>
:> >Or check fmax, with and without a reset.
:>
:> Hey, thank you all for answering!
:>
:> The fmax of a single SRL seems to be way beyond the
:> capacity of the global clock nets. (At least for Spartan2E, that is)
:>
:> If I do something like -
:>
:> p : process(clk) is
:> signal s1, s2 : std_logic;
:> begin
:> if clk'event and clk='1' then
:> s1 <= A;
:> s2 <= s1;
:> Q <= s2;
:> end if
:> end process;
:>
:> - I'll get an Fmax of 561Mhz on a XC2S50e-7 !!!
:> At least WP4.2's timing analyzer seems to think so...
:>
:> But anyway, I guess I'll stick to throwing FDE's at all that
:> nasty stuff coming from the outside...
:>
:> Regards Hans
:>
:> P.S:
:>
:> If you think, you found an easy way of doing something in VHDL,
:> you're probably doing it wrong. :eek:)
:>
:
 
On Mon, 17 Nov 2003 10:11:24 -0800, Peter Alfke <peter@xilinx.com>
wrote:

I concur. The SRL16 structure is different from a conventional
flip-flop. Although it is only the Master latch in a flip-flop that is
reponsible for metastability (the Slave just does the read-out), this
might imply that there is no difference. But I still would be leary to
venture into untested territory.
Click to expand...

Hi Hans-Juergen,
Try a search on Google groups "metastability srl". Top answer is a
discussion we had here called "Should I worry about metastability". Xilinx's
expert, Peter Alfke, said :-

I will not guarantee that SRL16s recover as fast from metastability as
the "normal" flip-flops that I documented, since SRLs are implemented in
a different circuit design. (Different might mean better or worse).
Click to expand...
Mike Tresseler wrote
Is there any difference w.r.t metastability in using SRLs
compared to FDs?

Don't know. Check the data sheet.

Or check fmax, with and without a reset.
Click to expand...
Hey, thank you all for answering!

The fmax of a single SRL seems to be way beyond the
capacity of the global clock nets. (At least for Spartan2E, that is)

If I do something like -

p : process(clk) is
signal s1, s2 : std_logic;
begin
if clk'event and clk='1' then
s1 <= A;
s2 <= s1;
Q <= s2;
end if
end process;

- I'll get an Fmax of 561Mhz on a XC2S50e-7 !!!
At least WP4.2's timing analyzer seems to think so...

But anyway, I guess I'll stick to throwing FDE's at all that
nasty stuff coming from the outside...

Regards Hans

P.S:

If you think, you found an easy way of doing something in VHDL,
you're probably doing it wrong. :eek:)
 
On Mon, 17 Nov 2003 23:55:06 GMT, "John_H" <johnhandwork@mail.com>
wrote:

You might find a comment elsewhere in your timing report that fmax is
limited by the SRL minimum pulse widths, Twph + Twpl. The 150E-7 timing I
had up on my screen (SpeedPrint, v6.1i timing) shows Twph of 2100 ps; Twpl
isn't specified in the SpeedPrint output but I recall it's the same as Twph
resulting in an SRL-limited fmax of 238 MHz with no jitter and 50.00% duty
cycle.

You might be able to get XST to avoid inferring s1 as part of the SRL by
specifying to XST that it's an IOB register, allowing s2 and Q to be an SRL
if XST so chooses.

If Q was to be your "stable" value and s1 and s2 were metastability
registers, why not use s2 as the stable, synchronized value? I thought only
two registers were needed for proper metastability protection, the output of
s1 being a "maybe" that settles to a high or low by the time s2 grabs the
value.


Thanks John, I have to admit that the timing analyzer output is still
Click to expand...
mostly obscure to me. I'm doing FPGAs more on a hobbyist level
in my spare time.

BTW. If you use s2 rather heavily, then XST might replicate it.

- Hans
 
The timing analyzer explains nothing about the gain-bandwidth product in
the latch feedback loop (the only thing that matters for metastable recovery).
Peter Alfke
======
Hans-Juergen Dorn wrote:

Thanks John, I have to admit that the timing analyzer output is still
mostly obscure to me. I'm doing FPGAs more on a hobbyist level
in my spare time.

BTW. If you use s2 rather heavily, then XST might replicate it.

- Hans
Click to expand...
 
But the timing analyzer does provide a message to the user that the fmax is
limited by the SRL (or CLB SelectRAM) write pulse width. I mentioned,
Hans-Juergen Dorn responded. He saw earlier that he'd "get an Fmax of
561Mhz on a XC2S50e-7" which I wanted to make sure he wouldn't try to rely
on.

I'd be ecstatic with that kind of SRL performance, but I'm designing with
registers for my own 260 MHz elements within a 2S150E.

But thanks for clearing up that the timing analyzer doesn't give additional
information that was pertinent to the earlier part of this thread.


"Peter Alfke" <peter@xilinx.com> wrote in message
news:3FBA5D7D.F7C79720@xilinx.com...
The timing analyzer explains nothing about the gain-bandwidth product in
the latch feedback loop (the only thing that matters for metastable
recovery).
Peter Alfke
======
Hans-Juergen Dorn wrote:

Thanks John, I have to admit that the timing analyzer output is still
mostly obscure to me. I'm doing FPGAs more on a hobbyist level
in my spare time.

BTW. If you use s2 rather heavily, then XST might replicate it.

- Hans
Click to expand...
 
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