SRL16 and IOBUF not Instantiated error!!

[Vick]

Hello All,

As said in earlier postings that I have this SDRAM Core (targetted for
Xilinx Virtex FPGA) available with me. I tried simulating the Verilog
code in Modelsim 5.8 SE. It results is an Error saying that SRL16,
IOBUF and couple of other modules were not instantiated. Now I have 2
questions related to this issue:

(1) Firstly, I am very surprised that if I have the entire "Core"
available then how come these modules are missing?

(2) Secondly, I believe these missing modules are the Synthesis
Constraints files. Researching on the internet I got the following
link on Xilinx: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0393_377.html

So can I use the SRL16 model given in the above link?

Thanx,
-V

 

[Jim Wu]

The simulation models are in $XILINX/verilog directory.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


"Vick" <iamyourengineer2004@hotmail.com> wrote in message
news:c373aa10.0411120436.6616841a@posting.google.com...

Hello All,

As said in earlier postings that I have this SDRAM Core (targetted for
Xilinx Virtex FPGA) available with me. I tried simulating the Verilog
code in Modelsim 5.8 SE. It results is an Error saying that SRL16,
IOBUF and couple of other modules were not instantiated. Now I have 2
questions related to this issue:

(1) Firstly, I am very surprised that if I have the entire "Core"
available then how come these modules are missing?

(2) Secondly, I believe these missing modules are the Synthesis
Constraints files. Researching on the internet I got the following
link on Xilinx:
http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0393_377.html

So can I use the SRL16 model given in the above link?

Thanx,
-V