sreadmemh question

[Sudhir D. Kadkade]

Hi all,

Is the following code supposed to work?

module try;
reg [0:3] mem [0:7];
reg [7*8-1:0] string;
initial begin
string[55:48] = 8'h35;
string[47:0] = 0;
$sreadmemh(mem, 3, 3, string);
for (i = 0; i < 8; i = i + 1) $display("%d -> %x", i, mem);
end
endmodule

Verilog-XL prints:
0 -> x
1 -> x
2 -> x
3 -> 5
4 -> x
5 -> x
6 -> x
7 -> x

However, NC-Verilog prints:
$sreadmem warning: words less than that given by address bounds
0 -> x
1 -> x
2 -> x
3 -> x
4 -> x
5 -> x
6 -> x
7 -> x

Regards,
Sudhir