SRAM bidirectional bus

[ALuPin]

Hi,

I have a question concerning the VHDL description of a bidirectional bus.

This bus comes from (goes to) an SRAM which I try to simulate with
a corresponding VHDL model.

Now I have an INOUT pin at my SRAM-Controller : Sram_data : inout(7 downto 0);

Within my SRAM-Controller I have the local signals
l_sram_data_out : std_logic_vector(7 downto 0);
l_sram_data_in : std_logic_vector(7 downto 0);


l_sram_data_out describes the data which I want to write into the SRAM.
l_sram_data_out is a registered signal.

l_sram_data_in describes the data I want to read from the SRAM.

The signal which is responsible for writing to the SRAM or reading out of
the SRAM is WE_bar.
WE_bar='0' & CS_bar='0' & OE_bar='1' ---> Write to the SRAM
WE_bar='1' & CS_bar='0' & OE_bar='0' ---> Read from the SRAM

How can I connect l_sram_data_out and l_sram_data_in
in a appropriate way to the bidirectional bus?

Does l_sram_data_in has to be synchronized? (It is used within the controller
in a synchronous environment)

I would appreciate any helpful hint.

Kind regards
André V.

 

[Michael Schöberl]

How can I connect l_sram_data_out and l_sram_data_in
in a appropriate way to the bidirectional bus?

My goal was to make Xilinx ISE use all the FF in the io-blocks ...
one ff for data_in, for the tristate-buffer and for data_out

the following has to be placed in the toplevel and was the
only way to make ISE do what I wanted ...

(Options: keep_hierarchy=true, use io-buffers=all/auto... can't
remember)



if clk'event and clk = 1 then
l_sram_data_in <= Sram_data;

if OE_bar = '1' then
Sram_data <= l_sram_data_out;
else
Sram_data <= (OTHERS => 'Z');
end if;
end if;


yes ... this produces latency ... but its synchronous



bye,
Michael

 

[Andy Peters]

Michael Schöberl <MSchoeberl@ratnet.stw.uni-erlangen.de> wrote in message news:<c1g6sr$1imo9d$1@ID-40811.news.uni-berlin.de>...

How can I connect l_sram_data_out and l_sram_data_in
in a appropriate way to the bidirectional bus?

My goal was to make Xilinx ISE use all the FF in the io-blocks ...
one ff for data_in, for the tristate-buffer and for data_out

the following has to be placed in the toplevel and was the
only way to make ISE do what I wanted ...

(Options: keep_hierarchy=true, use io-buffers=all/auto... can't
remember)



if clk'event and clk = 1 then
l_sram_data_in <= Sram_data;

if OE_bar = '1' then
Sram_data <= l_sram_data_out;
else
Sram_data <= (OTHERS => 'Z');
end if;
end if;


yes ... this produces latency ... but its synchronous

That works? The synthesis tool doesn't choke on the (others => 'Z')?

The usual way to do it is (sorry for Verilog here, also assume active
HIGH output enable):

assign Sram_data = OE ? l_sram_data_out : 'hz;

-a

 

[Michael Schöberl]

That works? The synthesis tool doesn't choke on the (others => 'Z')?

well - yes ...
there are a few things I should have mentioned:
- Im using Xilinx fpgas with ISE and XST.
- The signals are all std_logic_vector and Sram_data
should be std_logic_vector with INOUT
- (others => 'Z') is only a vhdl shortcut for "ZZZZZZZZZZZZ"

The usual way to do it is (sorry for Verilog here, also assume active
HIGH output enable):

assign Sram_data = OE ? l_sram_data_out : 'hz;

this looks similar to
Sram_data <= l_sram_data_out WHEN OE_bar = '1' ELSE (OTHERS => 'Z');

if you allow FFs to be placed in io-blocks then XST puts the
data-FFs in the iob ...
but if you take a close look at xilinx fpgas then you can see
another FF for controlling the Tristate-Buffer ... the only way
(I know) to make XST use this FF was the above description ...


bye,
Michael