SR latch is too easy?

[Kevin Kilzer]

I am new to Verilog, and I'm having trouble getting an SR latch to work.

Consider two signals:

---\____________/----- nCS
--------\____/----------- nSTB

I want to generate something that goes low at nSTB, then returns high at the end of nCS.

--------\_________/------ nSTRETCH


My Verilog looks like this:

wire nCS1000;
assign nCS1000 = (nRESET & ~nCS & ~A13 & A12)? 0 : 1;
assign nSTRETCH = nCS1000 ? 1'b1 : (~nSTB ? 1'b0 : nSTRETCH);

The actual nSTRETCH goes low on the first nSTB, and never goes high again.

All other signals are inputs to a Xilinx 95288 CPLD from a microprocessor (reset and address signals). nSTRETCH is an output pin
on the PLD.

Can anyone suggest where the problem might be?

Thanks.

Kevin

 

[Homuncilus]

On Apr 27, 7:47 pm, Kevin Kilzer <kkilzer.remove.t...@mindspring.com>
wrote:

I am new to Verilog, and I'm having trouble getting an SR latch to work.

Consider two signals:

---\____________/----- nCS
--------\____/----------- nSTB

I want to generate something that goes low at nSTB, then returns high at the end of nCS.

--------\_________/------ nSTRETCH

My Verilog looks like this:

wire nCS1000;
assign nCS1000 = (nRESET & ~nCS & ~A13 & A12)? 0 : 1;
assign nSTRETCH = nCS1000 ? 1'b1 : (~nSTB ? 1'b0 : nSTRETCH);

The actual nSTRETCH goes low on the first nSTB, and never goes high again.

All other signals are inputs to a Xilinx 95288 CPLD from a microprocessor (reset and address signals). nSTRETCH is an output pin
on the PLD.

Can anyone suggest where the problem might be?

Thanks.

Kevin

check out if the nCS1000 went high

 

[Kevin Kilzer]

On 28 Apr 2007 04:47:10 -0700, Homuncilus <Sha.Craig@gmail.com> wrote:

On Apr 27, 7:47 pm, Kevin Kilzer <kkilzer.remove.t...@mindspring.com
wrote:
I am new to Verilog, and I'm having trouble getting an SR latch to work.

Consider two signals:

---\____________/----- nCS
--------\____/----------- nSTB

I want to generate something that goes low at nSTB, then returns high at the end of nCS.

--------\_________/------ nSTRETCH

My Verilog looks like this:

wire nCS1000;
assign nCS1000 = (nRESET & ~nCS & ~A13 & A12)? 0 : 1;
assign nSTRETCH = nCS1000 ? 1'b1 : (~nSTB ? 1'b0 : nSTRETCH);

The actual nSTRETCH goes low on the first nSTB, and never goes high again.

All other signals are inputs to a Xilinx 95288 CPLD from a microprocessor (reset and address signals). nSTRETCH is an output pin
on the PLD.

Can anyone suggest where the problem might be?

Thanks.

Kevin

check out if the nCS1000 went high

I did look at that by changing nSTRETCH, and it worked as expected...
assign nSTRETCH = nCS1000;

Is it necessary to explicitly force priority? Like this...
assign nSTRETCH = (nCS1000 and nSTB) ? 1'b1 : (~nCS1000 and ~nSTB) ? 1'b0 : nSTRETCH);

Kevin

 

[gabor]

On Apr 30, 8:21 am, Kevin Kilzer <kkilzer.remove.t...@mindspring.com>
wrote:

On 28 Apr 2007 04:47:10 -0700, Homuncilus <Sha.Cr...@gmail.com> wrote:



On Apr 27, 7:47 pm, Kevin Kilzer <kkilzer.remove.t...@mindspring.com
wrote:
I am new to Verilog, and I'm having trouble getting an SR latch to work.

Consider two signals:

---\____________/----- nCS
--------\____/----------- nSTB

I want to generate something that goes low at nSTB, then returns high at the end of nCS.

--------\_________/------ nSTRETCH

My Verilog looks like this:

wire nCS1000;
assign nCS1000 = (nRESET & ~nCS & ~A13 & A12)? 0 : 1;
assign nSTRETCH = nCS1000 ? 1'b1 : (~nSTB ? 1'b0 : nSTRETCH);

The actual nSTRETCH goes low on the first nSTB, and never goes high again.

All other signals are inputs to a Xilinx 95288 CPLD from a microprocessor (reset and address signals). nSTRETCH is an output pin
on the PLD.

Can anyone suggest where the problem might be?

Thanks.

Kevin

check out if the nCS1000 went high

I did look at that by changing nSTRETCH, and it worked as expected...
assign nSTRETCH = nCS1000;

Is it necessary to explicitly force priority? Like this...
assign nSTRETCH = (nCS1000 and nSTB) ? 1'b1 : (~nCS1000 and ~nSTB) ? 1'b0 : nSTRETCH);

Kevin

I found no problems with your original code. I made
the following modules for testing:

module junk
(
nRESET,
nCS,
A13,
A12,
nSTB,
nSTRETCH
);

input nRESET, nCS, A13, A12, nSTB;
output nSTRETCH;

wire nCS1000;

assign nCS1000 = (nRESET & ~nCS & ~A13 & A12)? 0 : 1;

assign nSTRETCH = nCS1000 ? 1'b1 : (~nSTB ? 1'b0 : nSTRETCH);

endmodule

module junktest();
reg nRESET;
reg nCS;
reg A13;
reg A12;
reg nSTB;

wire nSTRETCH;

junk uut
(
.nRESET (nRESET),
.nCS (nCS),
.A13 (A13),
.A12 (A12),
.nSTB (nSTB),
.nSTRETCH (nSTRETCH)
);

initial begin
nRESET = 0;
nCS = 1;
A13 = 0;
A12 = 1;
nSTB = 1;
// Wait at least 100 nS for GSR to finish then do something...
#110 nRESET = 1;
#20 nCS = 0;
#20 nSTB = 0;
#10 nSTB = 1;
#20 nCS = 1;
end

endmodule

This simulated fine in ModelSim, and using XST (version 6.1)
it also simulated in the "Post-Fit" model, so theoretically it
should have built working hardware...

Are you sure your inputs are doing what you think?

Are you sure the signal isn't driven (held) low by some other
connection on your board?

What tools / version are you using to build the project?

Did you try to simulate it?

HTH,
Gabor