Spice model to check the status of internal signals

Hello, I'm designing an ASIC and have spice netlist for the design. My
input needs to change based on the status of the internal signal
generated on simulation dynamically. For example my input IN should go
to high or low based on the value of some internal signal X generated
on simulation ? How should I modify my spice to do the above task.
Thanks.

 

[mk]

On 22 Oct 2006 02:02:24 -0700, hsankara@gmail.com wrote:

Hello, I'm designing an ASIC and have spice netlist for the design. My
input needs to change based on the status of the internal signal
generated on simulation dynamically. For example my input IN should go
to high or low based on the value of some internal signal X generated
on simulation ? How should I modify my spice to do the above task.
Thanks.

Why would you simulate the ASIC in spice? Is it a mixed signal chip?
If not, just verilog with SDF would be enough. Anyway if you really
need to do it, you can put the logic at the top of your spice stack to
implement the functionality you need (ie if you need to invert the
input as the internal signal changes, put an inverter at the top and
connect the pins accordingly.). Then you may have to either propagate
the internal signal to the top through pins or use a hierarchical
reference depending on your spice simulator.

 

[Bernd Fischer]

For example my input IN should go
to high or low based on the value of some internal signal X generated
on simulation ? How should I modify my spice to do the above task.
Thanks.

How about a testbench with a feedback loop?!

Bernd