SPI slave problem

Hello Folks,
I'm writting a slave SPI code for my FPGA and very sure that
my master is generating the right SPI but somehow slave is unable to
decode it. I've never used the verilog before so it might be possible
that something is wrong with my code. Please advice.
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module test_spi(led,MOSI,SS,SCK,clk);

output [7:0] led;

input MOSI, SS, SCK, clk;

wire MOSI;
wire SS;
wire SCK;
wire clk;

reg num = 7;
reg [7:0] temp = 0;
reg SCK_LAST;
reg SCK_NOW;
reg [7:0] led;


always @(posedge clk)

begin
if (!SS)
begin
SCK_LAST = SCK_NOW;
SCK_NOW = SCK;
if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising
edge
begin
if (num < 8) // 8 bits counter
begin
if (!MOSI)
begin
temp = (temp << 1); //1 bit-shift and store it to temp when
receiving "0"
end
else
begin
temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp
when receiving "1"
end
if (num == 0)
begin
led = temp; //output to the LED on the board
num = 10;
end
end
end
num = num - 1;
end
else
begin
num = 7; //reset counter and temp store
temp = 8'b0;
end

end

endmodule

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Thanks for your time.

 

Hi.

I haven't tried compiling your code, but the biggest problem I see is
that "num" is only 1 bit wide. It looks like you set it to 10 at one
point, so it should be 4 bits wide, "reg [3:0] num".

I use Altera Quartus, and I don't think it allows initialization of
registers like the statement "reg [7:0]temp = 0". Typically there would
be a reset signal, which you would use to initialize registers.

I can provide more help if you want.

johnn


mankin18@gmail.com wrote:

Hello Folks,
I'm writting a slave SPI code for my FPGA and very sure that
my master is generating the right SPI but somehow slave is unable to
decode it. I've never used the verilog before so it might be possible
that something is wrong with my code. Please advice.
_________________________________________________________________________

module test_spi(led,MOSI,SS,SCK,clk);

output [7:0] led;

input MOSI, SS, SCK, clk;

wire MOSI;
wire SS;
wire SCK;
wire clk;

reg num = 7;
reg [7:0] temp = 0;
reg SCK_LAST;
reg SCK_NOW;
reg [7:0] led;


always @(posedge clk)

begin
if (!SS)
begin
SCK_LAST = SCK_NOW;
SCK_NOW = SCK;
if((SCK_LAST==0)&(SCK_NOW==1)) // check SCK is rising
edge
begin
if (num < 8) // 8 bits counter
begin
if (!MOSI)
begin
temp = (temp << 1); //1 bit-shift and store it to temp when
receiving "0"
end
else
begin
temp = ((temp << 1)|8'b00000001); //1 bit-shift and store it to temp
when receiving "1"
end
if (num == 0)
begin
led = temp; //output to the LED on the board
num = 10;
end
end
end
num = num - 1;
end
else
begin
num = 7; //reset counter and temp store
temp = 8'b0;
end

end

endmodule

_________________________________________________________________________


Thanks for your time.