K
khan
Guest
Hello i am writing code for spi slave module and i want to use only SCK provided by master block. I mean dont want to use system clock in Slave. So when write sequential logics can i write
always@(posedge SCK)
is it right as this is a slower (serial) clock povided by masters.
always@(posedge SCK)
is it right as this is a slower (serial) clock povided by masters.