SPI -- in Verilog ????...Help

Hi

I am a newbie in Verilog and have a question about how to setup a SPI
interface in my FPGA to talk to some DACs. people who are in this group
seems to be very knowledgeable and I am hoping some one can give me
some tips or helps.

briefly, here is what I have, my FPGA runs at 50MHz clk and I have a
counter( clock divider ) to generate my SPI clock(SCK) to send out to
the other device(DACs, etc). Then SPI should be a simple 8 or 16 bit
shift register. I know how to construct the shift register in Verilog.
but the problem is I have TWO clocks. my FPGA is running at 50MHz ( so
the FF on the shift register will be tied to this clock) and then I
have the slow SPI clock and I want to send the data out with....
What do I do?.. I can't just run everything inside the FPGA with a slow
SPI clock. and I can't send data out with the fast FPGA clock.... What
am I thinking wrong here? I thought about this for too long. there is
something I am missing!!????????

I appreciate all the help and tips.
Thank you
Ben

 

[johnp]

Ben -

Your slow SPI clock is generated from your 50Mhz clock.
You can make a simple circuit that will also create a pulse
before the SPI clock edge you're using for sifting data.

So...

always @(posedge clk50)
if (slow_pulse)
shift_reg <= {shift_reg, 1'b0}


This should give you enough of a hint to move forward.

John Providenza



Ben.Nader@gmail.com wrote:

Hi

I am a newbie in Verilog and have a question about how to setup a SPI
interface in my FPGA to talk to some DACs. people who are in this group
seems to be very knowledgeable and I am hoping some one can give me
some tips or helps.

briefly, here is what I have, my FPGA runs at 50MHz clk and I have a
counter( clock divider ) to generate my SPI clock(SCK) to send out to
the other device(DACs, etc). Then SPI should be a simple 8 or 16 bit
shift register. I know how to construct the shift register in Verilog.
but the problem is I have TWO clocks. my FPGA is running at 50MHz ( so
the FF on the shift register will be tied to this clock) and then I
have the slow SPI clock and I want to send the data out with....
What do I do?.. I can't just run everything inside the FPGA with a slow
SPI clock. and I can't send data out with the fast FPGA clock.... What
am I thinking wrong here? I thought about this for too long. there is
something I am missing!!????????

I appreciate all the help and tips.
Thank you
Ben

 

John...

Thank you for the tip. I got it working now.
Ben
johnp wrote:

Ben -

Your slow SPI clock is generated from your 50Mhz clock.
You can make a simple circuit that will also create a pulse
before the SPI clock edge you're using for sifting data.

So...

always @(posedge clk50)
if (slow_pulse)
shift_reg <= {shift_reg, 1'b0}


This should give you enough of a hint to move forward.

John Providenza



Ben.Nader@gmail.com wrote:
Hi

I am a newbie in Verilog and have a question about how to setup a SPI
interface in my FPGA to talk to some DACs. people who are in this group
seems to be very knowledgeable and I am hoping some one can give me
some tips or helps.

briefly, here is what I have, my FPGA runs at 50MHz clk and I have a
counter( clock divider ) to generate my SPI clock(SCK) to send out to
the other device(DACs, etc). Then SPI should be a simple 8 or 16 bit
shift register. I know how to construct the shift register in Verilog.
but the problem is I have TWO clocks. my FPGA is running at 50MHz ( so
the FF on the shift register will be tied to this clock) and then I
have the slow SPI clock and I want to send the data out with....
What do I do?.. I can't just run everything inside the FPGA with a slow
SPI clock. and I can't send data out with the fast FPGA clock.... What
am I thinking wrong here? I thought about this for too long. there is
something I am missing!!????????

I appreciate all the help and tips.
Thank you
Ben