SPI 4.2 Core perceptions and Power

D

Dan Schaffer

Guest
Has Anyone used the SPI 4.2 Core?
How well is it implemented?
Any idea of the power consumption? I'm wondering if the 2W specs on the web
site are valid.

Thanks,
Dan
 
Dan -

I assume you're talking about the Xilinx core from Modelware? I worked
on a project last year where we used the core in a Virtex2 on a
daughtercard to interface with and test the ASIC we built. I worked on
the ASIC SPI-4 interface and designed the boards, but I did not actually
do the SPI-4 FPGA work. I can't vouch for the power number, but it
sounds reasonable. It's very hard to isolate in a system beacause you
wrap a lot of logic around the core inside the FPGA. All in all the core
worked as advertised with the possible exception of dynamic alignment.
It's been out there for quite a while now. I personally wouldn't
hesitate to use it.

I forwarded your post to the engineer who did the FPGA work and his
edited response is below. The BGA connector he refers to is the
mezzanine connector between the ASIC and the daughtercard.

Good luck,

Robert

"We might have tried Dynamic Alignment once, but that was several SPI-4
core revisions ago. Otherwise, we've stuck with static alignment.

I haven't done any power measurements. Xilinx has a spreadsheet that
can calculate power based on the actual design file (ncd). But I bet
this is how
they came up with the 2Watt spec.

I am currently running the SPI cores (rx and tx) at 296MHz, which is
592MBit double data rate. We ran previously at 320MHz (640Mbit DDR),
but we were getting occasional SPI-4 DIP4 errors.
Even at the 296MHz rate, we've had to turn off the training patterns
that we send to the ASIC to get rid of SPI-4 framing errors. Sounds
like
it has difficulty distinguishing between data frames and training
patterns sometimes.

Adding dynamic alignment would not fix this, because that only applies
to the rx core. I wonder if going through the BGA connector is
aggravating the
problem. We haven't spent much time debugging this issue, because the
296MHz clock rate is sufficient for now."


"Dan Schaffer" <dan-schaffer@comcast.net> wrote in message
news:nwrub.236601$Tr4.696017@attbi_s03...
Has Anyone used the SPI 4.2 Core?
How well is it implemented?
Any idea of the power consumption? I'm wondering if the 2W specs on
the web
site are valid.

Thanks,
Dan
Click to expand...
 
test
"Robert Sefton" <rsefton@abc.net> wrote in message
news:bpekud$1n7t8i$1@ID-212988.news.uni-berlin.de...
Dan -

I assume you're talking about the Xilinx core from Modelware? I worked
on a project last year where we used the core in a Virtex2 on a
daughtercard to interface with and test the ASIC we built. I worked on
the ASIC SPI-4 interface and designed the boards, but I did not actually
do the SPI-4 FPGA work. I can't vouch for the power number, but it
sounds reasonable. It's very hard to isolate in a system beacause you
wrap a lot of logic around the core inside the FPGA. All in all the core
worked as advertised with the possible exception of dynamic alignment.
It's been out there for quite a while now. I personally wouldn't
hesitate to use it.

I forwarded your post to the engineer who did the FPGA work and his
edited response is below. The BGA connector he refers to is the
mezzanine connector between the ASIC and the daughtercard.

Good luck,

Robert

"We might have tried Dynamic Alignment once, but that was several SPI-4
core revisions ago. Otherwise, we've stuck with static alignment.

I haven't done any power measurements. Xilinx has a spreadsheet that
can calculate power based on the actual design file (ncd). But I bet
this is how
they came up with the 2Watt spec.

I am currently running the SPI cores (rx and tx) at 296MHz, which is
592MBit double data rate. We ran previously at 320MHz (640Mbit DDR),
but we were getting occasional SPI-4 DIP4 errors.
Even at the 296MHz rate, we've had to turn off the training patterns
that we send to the ASIC to get rid of SPI-4 framing errors. Sounds
like
it has difficulty distinguishing between data frames and training
patterns sometimes.

Adding dynamic alignment would not fix this, because that only applies
to the rx core. I wonder if going through the BGA connector is
aggravating the
problem. We haven't spent much time debugging this issue, because the
296MHz clock rate is sufficient for now."


"Dan Schaffer" <dan-schaffer@comcast.net> wrote in message
news:nwrub.236601$Tr4.696017@attbi_s03...
Has Anyone used the SPI 4.2 Core?
How well is it implemented?
Any idea of the power consumption? I'm wondering if the 2W specs on
the web
site are valid.

Thanks,
Dan
Click to expand...
 
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