S
sergio.pesenti@gmail.com
Guest
A spectreVerilog simulation which was working perfectly before now
fails in netlisting with an error message for each mixed-signal nets:
*USRERR: Net net063<10>, in module coco, lib chico, view schematic
requires the generation of Hierarchical Interface Element (IE) inside a
cellview having the view name that is a member of the analog or
digital stop view set. Such an IE will be ignored by the simulator.
Please change your design to avoid this limitation.
The config view is allright and the patitionning seems to work without
complain.
Does anybody have an idea of what I'm doing wrong or what to look at?
sergio
fails in netlisting with an error message for each mixed-signal nets:
*USRERR: Net net063<10>, in module coco, lib chico, view schematic
requires the generation of Hierarchical Interface Element (IE) inside a
cellview having the view name that is a member of the analog or
digital stop view set. Such an IE will be ignored by the simulator.
Please change your design to avoid this limitation.
The config view is allright and the patitionning seems to work without
complain.
Does anybody have an idea of what I'm doing wrong or what to look at?
sergio