Spectre Netlisting

[Guenther Sohler]

Hallo Group,

For characterizing pads with external scripts i want to get
a spectre netlist of my "device under test".

In analog artist, I clicked Simulation->Recreate Netlist to
spectre-netlist
my complete test-bench. My intent was to copy out the device under test
for further test.

Unfortunately my dut subcircuit looks very malformed. In the subckt header
I expect names like 'DI', 'DO' etc.

Why doesn't it look like this, and how can I fix it ?

rds


subckt my_pad _net0 _net1 _net2 _net3 _net4 IO _net5
_net6 VSSE VSSI ZI inh_gnd

 

[Andrew Beckett]

On Tue, 27 Sep 2005 16:46:14 +0200, Guenther Sohler
<guenther.sohler@newlogic.com> wrote:

Hallo Group,

For characterizing pads with external scripts i want to get
a spectre netlist of my "device under test".

In analog artist, I clicked Simulation->Recreate Netlist to
spectre-netlist
my complete test-bench. My intent was to copy out the device under test
for further test.

Unfortunately my dut subcircuit looks very malformed. In the subckt header
I expect names like 'DI', 'DO' etc.

Why doesn't it look like this, and how can I fix it ?

rds


subckt my_pad _net0 _net1 _net2 _net3 _net4 IO _net5
_net6 VSSE VSSI ZI inh_gnd

Guenther,

I'd guess that the nets called _net0 _net1 etc either have reserved name, or
clash with other instance names or parameter names in the design.

Currently the netlister maps names when you have a net/inst/param name clash -
although spectre now allows you to do this. This has been turned off in the
ICOA5251 release. It will still mapped reserved names though.

What are the names of the pins in the schematic, and do they clash with
something else?

Regards,

Andrew.

 

[Guenther Sohler]

Guenther,

I'd guess that the nets called _net0 _net1 etc either have reserved name, or
clash with other instance names or parameter names in the design.

Currently the netlister maps names when you have a net/inst/param name clash -
although spectre now allows you to do this. This has been turned off in the
ICOA5251 release. It will still mapped reserved names though.

What are the names of the pins in the schematic, and do they clash with
something else?

Regards,

Andrew.

Andrew, I dont know, what is changed, but when I started my cadence again
yesterday, it put the correct names. The names should be like "DPD" "DPU"
maybe it was a parameter name clash. I will check for it the next time, I
see it.

However, I see is no straight-forward way in cadence to create a complete
spectre netlist of your DUT in cadence:
If I open analog artist from the DUT-schematic and create the final
netlist, the subckt header is missing(and the simulator statement is extra)
when I open analog artist from the testbench, I have to delete the
testbench and the simulation statements ...


rds

 

[Andrew Beckett]

On Fri, 30 Sep 2005 09:53:41 +0200, Guenther Sohler
<guenther.sohler@newlogic.com> wrote:

Guenther,

I'd guess that the nets called _net0 _net1 etc either have reserved name, or
clash with other instance names or parameter names in the design.

Currently the netlister maps names when you have a net/inst/param name clash -
although spectre now allows you to do this. This has been turned off in the
ICOA5251 release. It will still mapped reserved names though.

What are the names of the pins in the schematic, and do they clash with
something else?

Regards,

Andrew.

Andrew, I dont know, what is changed, but when I started my cadence again
yesterday, it put the correct names. The names should be like "DPD" "DPU"
maybe it was a parameter name clash. I will check for it the next time, I
see it.

However, I see is no straight-forward way in cadence to create a complete
spectre netlist of your DUT in cadence:
If I open analog artist from the DUT-schematic and create the final
netlist, the subckt header is missing(and the simulator statement is extra)
when I open analog artist from the testbench, I have to delete the
testbench and the simulation statements ...


rds

Actually, if you ensure there is one level of hierarchy above, I guess that's
almost it? And you could pick the "netlist" file instead of "input.scs" - this
is missing all the analysis statements etc.

Spectre - in common with other circuit simulators - allows (and requires) top
level instances, hence the lack of a top level subckt.

Regards,

Andrew.