Spectre error

S

Saran

Guest
Hi,

I am just starting to gain experience on cadence tools. I am trying to
do a simulation using analog environment. This is a simple flip flop
written in verilog. I have imported that to schematic and then using
spectreverilog in analog enviroment. I am getting the following error
when I netlist and run the simulation...Can anyone guide me in the
right direction..

Thanks a lot

Regs,
Saran
____

Simulating `analog/input.scs' on vlsi32 at 2:56:46 PM, Sun Nov 7,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 26: Syntax error in specification of
`_ie99997'.

spectre terminated prematurely due to fatal error.

----
 
This is a repost...I am sorry...The last post for some reason was not
being displayed

Hi Andrew,

Here is the netlist...i am getting the error
Simulating `analog/input.scs' on vlsi32 at 1:53:39 PM, Tue Nov 9,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 29: Syntax error in specification of
`_ie99998'.

spectre terminated prematurely due to fatal error.
___

Thanks once again...
I am virutally stuck here..Not getting myself moving in the proper
direction. Any help would be greatly appreciated.

Netlist
___

// Generated for: spectre
// Generated on: Nov 9 13:34:27 2004
// Design library name: Saran_MS_Tut
// Design cell name: AOI_test
// Design view name: config
simulator lang=spectre
global 0
include "/usr/local/cadence/ic5141/tools.sun4v/dfII/samples/artist/ahdlLib/quantity.spectre"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16N.m"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16P.m"
// BEGIN Flat Interface Elements
// Flattened IE at /net5 uses port path 99999
// Flattened IE at /net11 uses port path 99998
// Flattened IE at /net7 uses port path 99997
// END Flat Interface Elements

// Library name: Saran_MS_Tut
// Cell name: AOI_test
// View name: schematic
// Inherited view list: spectre spice verilog behavioral functional
hdl
//system verilogNetlist schematic cmos.sch cmos_sch veriloga ahdl
V2 (net11 net4) vsource dc=0 type=dc
C0 (net4 0) capacitor c=10f
V1 (net5 0) vsource type=pulse val0=1 val1=5 width=20n
V0 (net7 0) vsource type=pulse val0=1 val1=5 width=10n
// BEGIN Hierarchical Interface Elements
_ie99997 (net7 0) a2d dest="99997" timex=1m vl=1.5 vh=3.5
_ie99998 (net11 0) d2a src="99998" fall=2n rise=3n val1=5 val0=0 valx=
\
valz=
_ie99999 (net5 0) a2d dest="99999" timex=1m vl=1.5 vh=3.5
// END Hierarchical Interface Elements
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12
temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
tran tran stop=200m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
save V2:p
saveOptions options save=allpub
___
 
I figured out the problem...Thanks.

Basically in the schematic, in the mixed signal menu, two interface
elements of the library were not specified. I had to specify them to
get it working. Everything works fine now. Thanks a lot for taking
time to suggest solutions to this problem.

Saran
 
Can you share that part of the netlist?

It's virtually impossible to tell without seeing more detail. Nothing
in your description gives any clue as to why this should happen,
because you don't appear to be doing anything out of the ordinary.

Regards,

Andrew.

On 7 Nov 2004 11:58:30 -0800, saranyan13@gmail.com (Saran) wrote:

Hi,

I am just starting to gain experience on cadence tools. I am trying to
do a simulation using analog environment. This is a simple flip flop
written in verilog. I have imported that to schematic and then using
spectreverilog in analog enviroment. I am getting the following error
when I netlist and run the simulation...Can anyone guide me in the
right direction..

Thanks a lot

Regs,
Saran
____

Simulating `analog/input.scs' on vlsi32 at 2:56:46 PM, Sun Nov 7,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 26: Syntax error in specification of
`_ie99997'.

spectre terminated prematurely due to fatal error.

----
Click to expand...
 
On 23 May 2005 08:21:13 -0700, "kvaddina" <kvaddina@yahoo.com> wrote:

Dear all,

I am trying to simulate a design. All works well with "spectreS"
simulator, but when it comes to "spectre" then I get an error.

*******
Error found by spectre during circuit read-in.
"input.scs" 8: Unable to open library file
`/opt/eda/xfab/spectre/xc06/xc06.scs'.
No such file or directory.

spectre terminated prematurely due to fatal error.
*******

I am using XFAB 0.6u technology and the folder xc06 corresponds to
that. I have checked that the library file xc06.scs file indeed does
not exist.

Why is it that it works well with "spectreS" and not with "spectre".
How could i make my design work for "spectre"? I am new to cadence.

Thanks in advance,
Kvaddina
Click to expand...
Whilst I'm not familiar with this particular xfab kit, the structure looks
similar to other XFAB kits that I've seen. Did you try reading any
documentation that came with the kit, or contacting XFAB themselves?

Regards,

Andrew.
 
In article <1116867338.991861.315720@g44g2000cwa.googlegroups.com>,
"kvaddina" <kvaddina@yahoo.com> wrote:

So i guess i have to work with spectreS. Any suggestions.
Click to expand...
From the stand of my knowledge, I am afraid you will have to. I tried
the same with the .8u XC, but had to accept the fact that XFab lag a bit
on their design kits. If it works, don't break it.



--
Svenn
 
On 23 May 2005 09:55:39 -0700, "kvaddina" <kvaddina@yahoo.com> wrote:

I have just checked out the documentaion. It has a link to "X-FAB
supported Design Programs". Here is the link to the screenshot.

http://www.aisl.cyd.liu.se/temp/screen.jpg

Unfortunately "spectre" is not there. But i could find "spectreS".

So i guess i have to work with spectreS. Any suggestions.
Click to expand...
Contact XFAB, as I suggested before. There seems to be support for spectre
direct in other kits from XFAB, so I'd expect that it would be possible with
this kit too - but you're best asking them that.

Regards,

Andrew.
 
From my knowledge this Kit of Xfab contain separated files for
transistor/cap/resistor.
You should include:
/opt/eda/xfab/spectre/xc06/bsism3v3.scs tm
/opt/eda/xfab/spectre/xc06/bip.scs tm
/opt/eda/xfab/spectre/xc06/cap.scs tm
/opt/eda/xfab/spectre/xc06/res.scs tm

into your model library setup.
(PS you can change tm for wp/ws for difference corner of the process)

"kvaddina" <kvaddina@yahoo.com> wrote in message
news:1116861673.327745.12800@g43g2000cwa.googlegroups.com...
Dear all,

I am trying to simulate a design. All works well with "spectreS"
simulator, but when it comes to "spectre" then I get an error.

*******
Error found by spectre during circuit read-in.
"input.scs" 8: Unable to open library file
`/opt/eda/xfab/spectre/xc06/xc06.scs'.
No such file or directory.

spectre terminated prematurely due to fatal error.
*******

I am using XFAB 0.6u technology and the folder xc06 corresponds to
that. I have checked that the library file xc06.scs file indeed does
not exist.

Why is it that it works well with "spectreS" and not with "spectre".
How could i make my design work for "spectre"? I am new to cadence.

Thanks in advance,
Kvaddina
Click to expand...
 
Hi,

we also work with xfab kits and we solved the problem by making a
xc06.scs by ourselves. You have to insert all existing *.scs files into
one xc06.scs in the same manner like the existing files built and put it
into you model path.

Frank.

kvaddina schrieb:
Hurray !! now it works. I have changed the ".cdsinit" file instead of
including the files in the "Model Library Setup" manually and it works
(for some wierd reason).

Thankyou all for your help.
Regards,
Kvaddina.
Click to expand...
 
Hi Andrew,

Here is the netlist...i am getting the error
Simulating `analog/input.scs' on vlsi32 at 1:53:39 PM, Tue Nov 9,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 29: Syntax error in specification of
`_ie99998'.

spectre terminated prematurely due to fatal error.
___

Thanks once again...
I am virutally stuck here..Not getting myself moving in the proper
direction. Any help would be greatly appreciated.

Netlist
___

// Generated for: spectre
// Generated on: Nov 9 13:34:27 2004
// Design library name: Saran_MS_Tut
// Design cell name: AOI_test
// Design view name: config
simulator lang=spectre
global 0
include "/usr/local/cadence/ic5141/tools.sun4v/dfII/samples/artist/ahdlLib/quantity.spectre"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16N.m"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16P.m"
// BEGIN Flat Interface Elements
// Flattened IE at /net5 uses port path 99999
// Flattened IE at /net11 uses port path 99998
// Flattened IE at /net7 uses port path 99997
// END Flat Interface Elements

// Library name: Saran_MS_Tut
// Cell name: AOI_test
// View name: schematic
// Inherited view list: spectre spice verilog behavioral functional
hdl
//system verilogNetlist schematic cmos.sch cmos_sch veriloga ahdl
V2 (net11 net4) vsource dc=0 type=dc
C0 (net4 0) capacitor c=10f
V1 (net5 0) vsource type=pulse val0=1 val1=5 width=20n
V0 (net7 0) vsource type=pulse val0=1 val1=5 width=10n
// BEGIN Hierarchical Interface Elements
_ie99997 (net7 0) a2d dest="99997" timex=1m vl=1.5 vh=3.5
_ie99998 (net11 0) d2a src="99998" fall=2n rise=3n val1=5 val0=0 valx=
\
valz=
_ie99999 (net5 0) a2d dest="99999" timex=1m vl=1.5 vh=3.5
// END Hierarchical Interface Elements
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12
temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
tran tran stop=200m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
save V2:p
saveOptions options save=allpub
___
 
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