Specifying a default value for a module input

Is there a way to define a default value for an input of a Verilog
module?

Example, I create a Counter module with an CountDown input whose
default is 0. If a user instantiate this module and does not specify
the CountDown input, it will be set by default to 0 such that the
counter does the expected thing of counting up (this is just an
example).

Thanks,

K.

 

[gabor]

kam...@hotmail.com wrote:

Is there a way to define a default value for an input of a Verilog
module?

Example, I create a Counter module with an CountDown input whose
default is 0. If a user instantiate this module and does not specify
the CountDown input, it will be set by default to 0 such that the
counter does the expected thing of counting up (this is just an
example).

Thanks,

K.

I don't know if it's the best way, but the Xilinx library
components accomplish this with a weak pullup
or pulldown wired to the input signal within the module.
HTH,
Gabor

 

[Kam]

Thanks for the response.

I am using Verilog/WebPack8.2 and Xilinx Spartan 3 so Xilinx specific
solutions are OK.

1. What is the syntax to specify the weak pull down?

2. Will the optimizers eventually eliminate the weak pulldown and will
replace it with a constant 1, constant 0 or a connection to a my bi
state net (no Z) when I instantiate the module?

Thanks,

K.

gabor wrote:

kam...@hotmail.com wrote:
Is there a way to define a default value for an input of a Verilog
module?

Example, I create a Counter module with an CountDown input whose
default is 0. If a user instantiate this module and does not specify
the CountDown input, it will be set by default to 0 such that the
counter does the expected thing of counting up (this is just an
example).

Thanks,

K.

I don't know if it's the best way, but the Xilinx library
components accomplish this with a weak pullup
or pulldown wired to the input signal within the module.
HTH,
Gabor