Specify-VerilogXL

[Steve Hamm]

Hello everyone

I am a beginner in Verilog and want to know how does Specify Blocks
work.

specify
in => out = 3;
endspecify

out = in & 1;

does it mean that in & 1 will be evaluated at t=3ns and then assigned to
out or in & 1 will be evaluated at t=0ns and then after 3ns it will be
assigned to out.


Thanks in advance for helping me.

Regards
Steve Hamm