Specify Blocks

[Pankaj Golani]

Hi

While simulating one of my circuits where the delays are specified in
specify blocks,I got an unexpected result.
The code is

module(out,in)

reg A;

specify
if (A) (in => out) = 3;
ensdspecify

lets say out = in & A;lets say in = 1;

so 3ns after A goes to 1 out = 1, but if A is a pulse of 2ns only then
will this statement work as I am getting out = 0,the reason i see that
may be it evaluates at t=3ns while it should evaluate at t=0 and then
delay the output by 3ns.

I hope i make myself clear.
Please help me regarding this.

Pankaj