Specify Blocks....Need help

[Steve Hamm]

Hello everyone

I am a beginner in Verilog and want to know how does Specify Blocks
work.

specify
in => out = 3;
endspecify

out = ~in;

does it mean that ~in will be evaluated at t=3ns and then assigned to
out or ~in will be evaluated at t=0ns and then after 3ns it will be
assigned to out.

Thanks ina advance for helping me

Regards
Steve Hamm