Specify Block

[Steve Hamm]

Hello everyone

I am a beginner in Verilog and want to know how does Specify Blocks
work.

specify
in => out = 3;
endspecify

out = in & 1;

does it mean that in & 1 will be evaluated at t=3ns and then assigned to
out or in & 1 will be evaluated at t=0ns and then after 3ns it will be
assigned to out.


Thanks in advance for helping me.

Regards
Steve Hamm

 

[Steven Sharp]

hamm_steve@yahoo.com (Steve Hamm) wrote in message news:<a4ea06c0.0408282137.5265c6a7@posting.google.com>...

specify
in => out = 3;
endspecify

out = in & 1;

I assume that you meant

assign out = in & 1;

does it mean that in & 1 will be evaluated at t=3ns and then assigned to
out or in & 1 will be evaluated at t=0ns and then after 3ns it will be
assigned to out.

Assuming a continuous assignment, it means that "in & 1" will be evaluated
any time "in" changes (call it time N). That value will be assigned to out
after 3 time units of delay (time N+3). The size of a time unit depends on
the setting of the timescale.

These delays are transport delays, but a simulator may provide options to
perform rejection of narrow pulses (usually as a percentage of the delay).
If the pulse rejection setting defaults to 100 percent, then the effect is
the same as inertial delay.

 

[David Roberts]

On Sat, 28 Aug 2004 22:37:37 -0700, Steve Hamm wrote:

Hello everyone

I am a beginner in Verilog and want to know how does Specify Blocks
work.

specify
in => out = 3;
endspecify

out = in & 1;

does it mean that in & 1 will be evaluated at t=3ns and then assigned to
out or in & 1 will be evaluated at t=0ns and then after 3ns it will be
assigned to out.

The evaluation occures when ever the inputs change. If a
new output value is detected the output will be scheduled
to change after the requested delay. As in your example
above at t=0ns out is detected to change. The value scheduled
to change 3ns later.

--David Roberts

Thanks in advance for helping me.

Regards
Steve Hamm