SpartanXL

R

rickman

Guest
I had a meeting with my local salesperson, rep and FAE and they got me
to take another look at the SpartanXL for the 5 volt tolerant socket on
my board. The part looks pretty good in most respects, but there are
two flies in the ointment. One is the lack of support in the current
tools. I know Xilinx still provides the "classic" tool set which should
work ok, but I am not comfortable using a different tool and would have
to buy a third party synthesis tool to support this.

The other problem is that I would have to use the XCS40XL-5CS280 to get
the density in a small package. But they don't offer an industrial temp
version in this package. Is there a thermal reason that this package
won't support the industrial temp range, or is this just a matter of
space on the shelf for yet another chip version? Any way to get around
this issue? Is there a spread sheet for calculating the power
consumption? I have a design that I can extract data from to drive a
power consumption model if I can get a model.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,
SpartanXL is an XC4000XL-derivative, while Spartan-II is Virtex-derived.
That means it is a big generation-step younger, more modern, better supported.
All the devices mentioned have 3.3V I/O that are 5-V tolerant. Take a
look at the younger parts, they may give you more flexibility. I hate to
contradict your FAE :-(

Peter Alfke
=============
rickman wrote:
I had a meeting with my local salesperson, rep and FAE and they got me
to take another look at the SpartanXL for the 5 volt tolerant socket on
my board. The part looks pretty good in most respects, but there are
two flies in the ointment. One is the lack of support in the current
tools. I know Xilinx still provides the "classic" tool set which should
work ok, but I am not comfortable using a different tool and would have
to buy a third party synthesis tool to support this.

The other problem is that I would have to use the XCS40XL-5CS280 to get
the density in a small package. But they don't offer an industrial temp
version in this package. Is there a thermal reason that this package
won't support the industrial temp range, or is this just a matter of
space on the shelf for yet another chip version? Any way to get around
this issue? Is there a spread sheet for calculating the power
consumption? I have a design that I can extract data from to drive a
power consumption model if I can get a model.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
 
Peter, thanks, but we have had this conversation several times. None of
the Virtex or Spartan II devices can be used in this socket because of
the high start up currents.

Right now the socket is slated to be filled by an Altera EP1K30 since it
meets all the requirements. I was looking at the SpartanXL only because
there would be some advantage to having all the PLDs on the board be
from one vendor using one tool. But I don't see much advantage to using
the SpXL if I have to use the "classic" tools and go with a large
package.


Peter Alfke wrote:
Rick,
SpartanXL is an XC4000XL-derivative, while Spartan-II is Virtex-derived.
That means it is a big generation-step younger, more modern, better supported.
All the devices mentioned have 3.3V I/O that are 5-V tolerant. Take a
look at the younger parts, they may give you more flexibility. I hate to
contradict your FAE :-(

Peter Alfke
=============
rickman wrote:

I had a meeting with my local salesperson, rep and FAE and they got me
to take another look at the SpartanXL for the 5 volt tolerant socket on
my board. The part looks pretty good in most respects, but there are
two flies in the ointment. One is the lack of support in the current
tools. I know Xilinx still provides the "classic" tool set which should
work ok, but I am not comfortable using a different tool and would have
to buy a third party synthesis tool to support this.

The other problem is that I would have to use the XCS40XL-5CS280 to get
the density in a small package. But they don't offer an industrial temp
version in this package. Is there a thermal reason that this package
won't support the industrial temp range, or is this just a matter of
space on the shelf for yet another chip version? Any way to get around
this issue? Is there a spread sheet for calculating the power
consumption? I have a design that I can extract data from to drive a
power consumption model if I can get a model.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
rickman <spamgoeshere4@yahoo.com> wrote:
: Peter, thanks, but we have had this conversation several times. None of
: the Virtex or Spartan II devices can be used in this socket because of
: the high start up currents.

For Spartan II the specifications for the startup current for recent silicon
has been revised some days ago. Do they still not meet your requirements.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
rickman <spamgoeshere4@yahoo.com> wrote:
: Peter, thanks, but we have had this conversation several times. None of
: the Virtex or Spartan II devices can be used in this socket because of
: the high start up currents.

For Spartan II the specifications for the startup current for recent silicon
has been revised some days ago. Do they still not meet your requirements?

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
 
Uwe Bonnes wrote:
rickman <spamgoeshere4@yahoo.com> wrote:
: Peter, thanks, but we have had this conversation several times. None of
: the Virtex or Spartan II devices can be used in this socket because of
: the high start up currents.

For Spartan II the specifications for the startup current for recent silicon
has been revised some days ago. Do they still not meet your requirements.
Click to expand...
Interesting. I see the Spartan IIE also had a tweak downwards,
and gained on dV/dT caveats.
MAX static currents are still not nice.

-jg
 
Uwe Bonnes wrote:
rickman <spamgoeshere4@yahoo.com> wrote:
: Peter, thanks, but we have had this conversation several times. None of
: the Virtex or Spartan II devices can be used in this socket because of
: the high start up currents.

For Spartan II the specifications for the startup current for recent silicon
has been revised some days ago. Do they still not meet your requirements.
Click to expand...
No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the
industrial temp range. This would require the power converter to be
larger than the chip! This section of the board is our "low power"
section and the power converter will supply a *total* of 250 mA at 2.5
volts.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Jim,

Various changes went into the new mask for the 300mm fab, so we were able to
reduce (by design) the start up peak by more than 60%. This also allows for
relaxing the dV/dt. SInce we figured out what causes this in Virtex II, we have
had no POS (power on surge) issues in subsequent families. Unfortunately it
required a complete redesign which is not possible for the older parts.

Austin

Jim Granville wrote:

Uwe Bonnes wrote:

rickman <spamgoeshere4@yahoo.com> wrote:
: Peter, thanks, but we have had this conversation several times. None of
: the Virtex or Spartan II devices can be used in this socket because of
: the high start up currents.

For Spartan II the specifications for the startup current for recent silicon
has been revised some days ago. Do they still not meet your requirements.

Interesting. I see the Spartan IIE also had a tweak downwards,
and gained on dV/dT caveats.
MAX static currents are still not nice.

-jg
Click to expand...
 
rickman wrote:
No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the
industrial temp range. This would require the power converter to be
larger than the chip! This section of the board is our "low power"
section and the power converter will supply a *total* of 250 mA at 2.5
volts.
Click to expand...
Did you see Austin Lesea's cunning trick of cycling the
chip until it warms up and starts on lower power?
 
Rick,

I understand. Industrial temp minimum current to power on cleanly is the toughest
part of the specification, even with the mask changes that were made to improve
things.

The app note on the "kick start" circuit is the only other alternative we can
offer. Storing up the charge required to supply the 1.5A does however require a
fairly large capacitor, and it gets even larger and tougher at -40C where almost
all caps are -30% to -80% less C (as the electrolyte freezes).

Austin
 
Tim wrote:
rickman wrote:
No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the
industrial temp range. This would require the power converter to be
larger than the chip! This section of the board is our "low power"
section and the power converter will supply a *total* of 250 mA at 2.5
volts.

Did you see Austin Lesea's cunning trick of cycling the
chip until it warms up and starts on lower power?
Click to expand...
I am selling boards to OEM customers. Do you really think it will look
good to recommend that they continue to cycle the FPGA until it warms
up? That could easily take seconds when the board should be ready to
come up in milliseconds. If the user is running on battery and needs to
process for a few ms, this will drain the battery very quickly.

Xilinx has a pattern of building problems into their chips which they
claim is the inevitable price of progress and expecting the users to
deal with them. In this case it turned out that it was not inevitable
since they fixed the problem with later, more advanced families.

Another issue that is being touted as "inevitable" is the increase in
static Icc to becoming greater than the dynamic current. But I can
assure you that this will be licked. Advances in transistor design are
being made that will allow 65 nm chips to maintain an acceptable level
of static Icc. If you don't believe me ask Intel about double and
triple gates.

Thanks for the warm up idea, but it is not workable in this situation.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,

Hey, we admit the high POS current in Virtex, Virtex E, Spartan II, and
Sparatan IIE, and we are proud that we got rid of it in subsequent families.
It is not "inevitable."

If you want to have a 200 MHz Fmax part instead of a 500 MHz Fmax part, we can
make the leakage much, much lower. No one seems to want a slower part, even
though it may costs a whole lot less.

As for transistor design techniques that reduce leakage, no one has found one
that works yet.

Hi_K gate oxide does not reduce d-s leakage, SOI does not reduce d-s leakage,
so about the only thing to do is to raise the Vt (relative to the Vcc), which
makes things slower. Anyone can do that.

Austin

rickman wrote:

Tim wrote:

rickman wrote:
No, the requirement only dropped from 2.0 Amps to 1.5 Amps at the
industrial temp range. This would require the power converter to be
larger than the chip! This section of the board is our "low power"
section and the power converter will supply a *total* of 250 mA at 2.5
volts.

Did you see Austin Lesea's cunning trick of cycling the
chip until it warms up and starts on lower power?

I am selling boards to OEM customers. Do you really think it will look
good to recommend that they continue to cycle the FPGA until it warms
up? That could easily take seconds when the board should be ready to
come up in milliseconds. If the user is running on battery and needs to
process for a few ms, this will drain the battery very quickly.

Xilinx has a pattern of building problems into their chips which they
claim is the inevitable price of progress and expecting the users to
deal with them. In this case it turned out that it was not inevitable
since they fixed the problem with later, more advanced families.

Another issue that is being touted as "inevitable" is the increase in
static Icc to becoming greater than the dynamic current. But I can
assure you that this will be licked. Advances in transistor design are
being made that will allow 65 nm chips to maintain an acceptable level
of static Icc. If you don't believe me ask Intel about double and
triple gates.

Thanks for the warm up idea, but it is not workable in this situation.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
 
Austin Lesea wrote:
Rick,

Hey, we admit the high POS current in Virtex, Virtex E, Spartan II, and
Sparatan IIE, and we are proud that we got rid of it in subsequent families.
It is not "inevitable."

If you want to have a 200 MHz Fmax part instead of a 500 MHz Fmax part, we can
make the leakage much, much lower. No one seems to want a slower part, even
though it may costs a whole lot less.
Click to expand...
Wow - Who have you asked ?

In the CPLD sector, the 'bragging rights slugfests' are over uA
standby,
not MHz. ( see lattice web site - I did note they pitch uA only,
and avoid uA/MHz, so perhaps they come (close) second on that one :)

As for transistor design techniques that reduce leakage, no one has found one
that works yet.
Click to expand...
A sweeping, and thus rather brave, statement ?

I assume Xilinx is already using mixed threshold design, at least ?

Hi_K gate oxide does not reduce d-s leakage, SOI does not reduce d-s leakage,
so about the only thing to do is to raise the Vt (relative to the Vcc), which
makes things slower. Anyone can do that.
Click to expand...
Look at the latest Transmeta processor. Extremely MHz focused company,
but
they can get to 2mW I think ?
Press release mentions something about licensing the IP...

-jg
 
Jim,

The easy ways are all taken. To use more than one oxide or more than one threshold
vt is just using last years technology where you can squeeze it in. There are no
new physical transistors that have been made that look like anything other than PhD
projects....

I don't speak CPLDs, so uA is something I have no understanding of.....

as for the "Ef-fishy-on" they are using a back well bias technique (already patented
by us and also separately by IBM, among others) that makes things slower where one
can get away with it (under programmable cell controls).

If you use a standard CMOS process, you are only able to bias up the nmos, or the
pmos wells, (not both), so unless you have a triple well process you can't really
push this technique as far as one would like.

Making the FPGA slower where you can get away with it is a far more difficult task
than a uP. I can just see the software tool error message now: "unknown constraint
- can not apply 'slow' attribute to this block"

Not brave, but not stupid either,

Austin



Jim Granville wrote:

Austin Lesea wrote:

Rick,

Hey, we admit the high POS current in Virtex, Virtex E, Spartan II, and
Sparatan IIE, and we are proud that we got rid of it in subsequent families.
It is not "inevitable."

If you want to have a 200 MHz Fmax part instead of a 500 MHz Fmax part, we can
make the leakage much, much lower. No one seems to want a slower part, even
though it may costs a whole lot less.

Wow - Who have you asked ?

In the CPLD sector, the 'bragging rights slugfests' are over uA
standby,
not MHz. ( see lattice web site - I did note they pitch uA only,
and avoid uA/MHz, so perhaps they come (close) second on that one :)


As for transistor design techniques that reduce leakage, no one has found one
that works yet.

A sweeping, and thus rather brave, statement ?

I assume Xilinx is already using mixed threshold design, at least ?


Hi_K gate oxide does not reduce d-s leakage, SOI does not reduce d-s leakage,
so about the only thing to do is to raise the Vt (relative to the Vcc), which
makes things slower. Anyone can do that.

Look at the latest Transmeta processor. Extremely MHz focused company,
but
they can get to 2mW I think ?
Press release mentions something about licensing the IP...

-jg
Click to expand...
 
Before I close the door on this, I want to take one last look at using
the SpartanXL for this socket. Right now there are several reasons not
to use the part, but only one is a show stopper. That is the lack of an
industrial temp part in the CS280 package. Looking at other lines, I
see that there is nothing inherent about the package that precludes
this.

So what would it take for me to use a commercial temp part, say the
XCS40XL-5CS280C and use it over an industrial temp range? If I scaled
my timing requirements by say, 33%, would that give me enough margin
over the industrial temp range?

Of course the other issues are not trivial. List price is way up there,
the lack of support in the ISE tools will require me to buy a $5000
synthesis tool, and I am still a little leary of designing in such an
old part to a product line that may have a lifetime of 8 years.

I recall working with one of these parts some 6 or 7 years ago. The
toolset from Xilinx included synthesis, IIRC. Is that package no longer
available?

I see in the archives here that the quiescent current for the SpartanXL
is very low, much lower than the data sheet number. But I can't find a
clear statement about the startup current. The data sheet says 100 mA
(which should not be a problem) but I wanted to know if this is much
lower in current chips.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
I rummaged around and found the old distribution of Foundation 1.5i that
I had used to design with a 4000XL back in 1998 using VHDL. Will this
package support the SpartanXL? I see that the version currently
provided by Xilinx is ISE 4.2i. When was this package orginally
released?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
Rick,

The startup current is very small, probably less than 20 mA. The 50 mA
number was a good number over PVT.

As for speed at temp, the part is probably the last one to have a classic
design of CLBs and interconnect (No DLL, No other "fancy features") so some
of the old "rules of thumb" for CMOS logic performance vs. temperature still
apply to it. Maybe Peter can help us here with some rule of thumb numbers
for plain 'ole CMOS logic.

If you open a case on the hotline with your specifc tool and support
question, you will get an answer quickly.

Austin

rickman wrote:

Before I close the door on this, I want to take one last look at using
the SpartanXL for this socket. Right now there are several reasons not
to use the part, but only one is a show stopper. That is the lack of an
industrial temp part in the CS280 package. Looking at other lines, I
see that there is nothing inherent about the package that precludes
this.

So what would it take for me to use a commercial temp part, say the
XCS40XL-5CS280C and use it over an industrial temp range? If I scaled
my timing requirements by say, 33%, would that give me enough margin
over the industrial temp range?

Of course the other issues are not trivial. List price is way up there,
the lack of support in the ISE tools will require me to buy a $5000
synthesis tool, and I am still a little leary of designing in such an
old part to a product line that may have a lifetime of 8 years.

I recall working with one of these parts some 6 or 7 years ago. The
toolset from Xilinx included synthesis, IIRC. Is that package no longer
available?

I see in the archives here that the quiescent current for the SpartanXL
is very low, much lower than the data sheet number. But I can't find a
clear statement about the startup current. The data sheet says 100 mA
(which should not be a problem) but I wanted to know if this is much
lower in current chips.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
 
The traditional view was that delays increase at a rate of 0.25% per
degree C.
With Industrial being nominally 15 degr hotter than Comm, this would
mean a 4% loss in speed at the hot end.
We gave the ususal warnings: "Not guaranteed since not tested," but I
never heard any complaints.
I have never heard about a Comm part failing functionally at Ind
temperature. But the speed loss is real.

If your part is running hot,
and Industrial it's not,
use this factor to derate
and let's finish the debate.

Peter Alfke
===========================
Austin Lesea wrote:
Rick,

The startup current is very small, probably less than 20 mA. The 50 mA
number was a good number over PVT.

As for speed at temp, the part is probably the last one to have a classic
design of CLBs and interconnect (No DLL, No other "fancy features") so some
of the old "rules of thumb" for CMOS logic performance vs. temperature still
apply to it. Maybe Peter can help us here with some rule of thumb numbers
for plain 'ole CMOS logic.

If you open a case on the hotline with your specifc tool and support
question, you will get an answer quickly.

Austin

rickman wrote:

Before I close the door on this, I want to take one last look at using
the SpartanXL for this socket. Right now there are several reasons not
to use the part, but only one is a show stopper. That is the lack of an
industrial temp part in the CS280 package. Looking at other lines, I
see that there is nothing inherent about the package that precludes
this.

So what would it take for me to use a commercial temp part, say the
XCS40XL-5CS280C and use it over an industrial temp range? If I scaled
my timing requirements by say, 33%, would that give me enough margin
over the industrial temp range?

Of course the other issues are not trivial. List price is way up there,
the lack of support in the ISE tools will require me to buy a $5000
synthesis tool, and I am still a little leary of designing in such an
old part to a product line that may have a lifetime of 8 years.

I recall working with one of these parts some 6 or 7 years ago. The
toolset from Xilinx included synthesis, IIRC. Is that package no longer
available?

I see in the archives here that the quiescent current for the SpartanXL
is very low, much lower than the data sheet number. But I can't find a
clear statement about the startup current. The data sheet says 100 mA
(which should not be a problem) but I wanted to know if this is much
lower in current chips.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
 
rickman wrote:
So what would it take for me to use a commercial temp part, say the
XCS40XL-5CS280C and use it over an industrial temp range? If I scaled
my timing requirements by say, 33%, would that give me enough margin
over the industrial temp range?
Click to expand...
Atmel, in their CPLD data state this :

# Using “C” Product for Industrial
#To use commercial product for industrial temperature ranges,
#down-grade one speed grade from the “I” to the “C” device
#(7 ns “C” = 10 ns “I”) and de-rate power by 30%.

Power here means thermal margin, due to higher Ta.
So long as the self-heating is not significant, you will
be well under Tj limits. I don't think you are pushing the MHz :)

-jg
 
1.5i was released in late 1998 (see http://www.xilinx.com/prs_rls/1_5i.htm)
and supported Spartan-XL. 4.2i was released in early 2002 (see
http://www.xilinx.com/prs_rls/software/0226_Em_perf.html)

rickman wrote:

I rummaged around and found the old distribution of Foundation 1.5i that
I had used to design with a 4000XL back in 1998 using VHDL. Will this
package support the SpartanXL? I see that the version currently
provided by Xilinx is ISE 4.2i. When was this package orginally
released?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Click to expand...
--
Marc Baker
Xilinx Applications
(408) 879-5375
 
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