Spartan3DSP TphDCM spec question

M

Mawa_fugo

Guest
1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns

2) What does that means when they say

"When the hold time is negative, it is possible to change the data
before the clock's active edge"

----------------------------------------------------------

What I read out from the above is that, the device does not require
the hold time at all ...Am I correct or...?
 
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote:

1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns

2) What does that means when they say

"When the hold time is negative, it is possible to change the data
before the clock's active edge"

----------------------------------------------------------

What I read out from the above is that, the device does not require the
hold time at all ...Am I correct or...?
Click to expand...
It means that the data can change no more than 0.26ns before the clock
edge -- and that means that the data must be _valid_ at that point, not
already meandering across the thresholds. It _doesn't_ mean that there's
no hold time requirement at all -- just that the hold time requirement is
a bit weird.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
 
On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote:
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote:
1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns

2) What does that means when they say

"When the hold time is negative, it is possible to change the data
before the clock's active edge"

 ----------------------------------------------------------

What I read out from the above is that, the device does not require the
hold time at all ...Am I correct or...?

It means that the data can change no more than 0.26ns before the clock
edge -- and that means that the data must be _valid_ at that point, not
already meandering across the thresholds.  It _doesn't_ mean that there's
no hold time requirement at all -- just that the hold time requirement is
a bit weird.

--
Tim Wescott
Control system and signal processing consultingwww.wescottdesign.com
Click to expand...
But then, that sounds very the same as the traditional setup time ???

Now its really weird & confuse. We have now two names to describe
the same thing? and the same paper calls out 2 different numbers for
the same thing

hmmm
???
 
Mawa_fugo wrote:
On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote:
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote:
1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns
2) What does that means when they say
"When the hold time is negative, it is possible to change the data
before the clock's active edge"
----------------------------------------------------------
What I read out from the above is that, the device does not require the
hold time at all ...Am I correct or...?
It means that the data can change no more than 0.26ns before the clock
edge -- and that means that the data must be _valid_ at that point, not
already meandering across the thresholds. It _doesn't_ mean that there's
no hold time requirement at all -- just that the hold time requirement is
a bit weird.

--
Tim Wescott
Control system and signal processing consultingwww.wescottdesign.com

But then, that sounds very the same as the traditional setup time ???

Now its really weird & confuse. We have now two names to describe
the same thing? and the same paper calls out 2 different numbers for
the same thing

hmmm
???





To be a little clearer, hold time is different from setup in that it
Click to expand...
defines the end of the data sampling window, while set defines the
start of the window. What Tim meant by "no more than 0.26ns before
the clock" is that the end of the valid window must not come *sooner*
than 0.26 ns before the clock. So if the data is stable until 0.26
ns before the clock and *then* starts to change, you will sample the
data in its stable state.

Negative numbers are a little perplexing because the definition of
setup and hold are referenced in a different direction, based on
the outdated assumption that a flip-flop's sampling window includes
the clock edge. So for that case both setup and hold would be positive.
For FPGA's, the actual data sampling window of a filp-flop is tiny,
and the bulk of the setup and hold requirements are due to the
delays in routing the signal and clock to the flip-flop's D
and CLK inputs. Since either the clock or the data signal can
have a longer routing delay, it's quite easy to end up with
either negative set or negative hold times.

So think of it this way:

The clock arrives at time T.
Data must be stable from time (T - setup) until time (T + hold).
If setup is positive and hold is negative, then the stable window
will be entirely before the clock edge:
CLK --------T-----------
Data xx<===>xxxxxxxxxxxxx
If hold is positive and setup is negative, the stable window will
be entirely after the clock edge.
CLK --------T-----------
Data xxxxxxxxxxxx<===>xxx
If both setup and hold are positive, then the stable window includes
the clock edge.
CLK --------T-----------
Data xxxxxx<===>xxxxxxxxx

HTH,
Gabor
 
On Thu, 07 Jul 2011 10:18:00 -0700, Mawa_fugo wrote:

On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote:
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote:
1) Why the spec calls out negative number for input holding time ?
eg. TphDCM = - 0.26 ns

2) What does that means when they say

"When the hold time is negative, it is possible to change the data
before the clock's active edge"

 ----------------------------------------------------------

What I read out from the above is that, the device does not require
the hold time at all ...Am I correct or...?

It means that the data can change no more than 0.26ns before the clock
edge -- and that means that the data must be _valid_ at that point, not
already meandering across the thresholds.  It _doesn't_ mean that
there's no hold time requirement at all -- just that the hold time
requirement is a bit weird.

--
Tim Wescott
Control system and signal processing consultingwww.wescottdesign.com

But then, that sounds very the same as the traditional setup time ???
Click to expand...
No. You may change the data before, but not after, the setup time.
You may change the data after the hold time, but not before it (i.e. not
between the setup and hold time).

A small negative hold time can result from a delay internal to the FF on
the data input, which is greater than any similar delay on the clock
input.

There will be a window before this hold time (but after the setup time)
during which you cannot change the data. SO if the hold time is -0.25ns,
there will be a setup time of greater than 0.25ns, (e.g. 0.5ns) and a
window between 0.5 and 0.25ns before the clock edge when the data must be
stable.

This can be a deliberate design feature to guarantee that pipelines will
avoid races in the presence of small amounts of clock skew, without
having to specify minimum routing delays between pipe stages.

(Timing analysis will still have to guarantee maximum delays, for a
particular clock frequency)

- Brian
 
On 07/07/2011 02:40 PM, Gabor wrote:
Mawa_fugo wrote:
On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote:
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote:
1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns
2) What does that means when they say
"When the hold time is negative, it is possible to change the data
before the clock's active edge"
----------------------------------------------------------
What I read out from the above is that, the device does not require the
hold time at all ...Am I correct or...?
It means that the data can change no more than 0.26ns before the clock
edge -- and that means that the data must be _valid_ at that point, not
already meandering across the thresholds. It _doesn't_ mean that there's
no hold time requirement at all -- just that the hold time
requirement is
a bit weird.

--
Tim Wescott
Control system and signal processing consultingwww.wescottdesign.com

But then, that sounds very the same as the traditional setup time ???

Now its really weird & confuse. We have now two names to describe
the same thing? and the same paper calls out 2 different numbers for
the same thing

hmmm
???





To be a little clearer, hold time is different from setup in that it
defines the end of the data sampling window, while set defines the
start of the window. What Tim meant by "no more than 0.26ns before
the clock" is that the end of the valid window must not come *sooner*
than 0.26 ns before the clock. So if the data is stable until 0.26
ns before the clock and *then* starts to change, you will sample the
data in its stable state.

Negative numbers are a little perplexing because the definition of
setup and hold are referenced in a different direction, based on
the outdated assumption that a flip-flop's sampling window includes
the clock edge. So for that case both setup and hold would be positive.
For FPGA's, the actual data sampling window of a filp-flop is tiny,
and the bulk of the setup and hold requirements are due to the
delays in routing the signal and clock to the flip-flop's D
and CLK inputs. Since either the clock or the data signal can
have a longer routing delay, it's quite easy to end up with
either negative set or negative hold times.

So think of it this way:

The clock arrives at time T.
Data must be stable from time (T - setup) until time (T + hold).
If setup is positive and hold is negative, then the stable window
will be entirely before the clock edge:
CLK --------T-----------
Data xx<===>xxxxxxxxxxxxx
If hold is positive and setup is negative, the stable window will
be entirely after the clock edge.
CLK --------T-----------
Data xxxxxxxxxxxx<===>xxx
If both setup and hold are positive, then the stable window includes
the clock edge.
CLK --------T-----------
Data xxxxxx<===>xxxxxxxxx
Click to expand...
Now, a chip that had both setup and hold times that were negative --
that would be astounding.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
On 07/07/2011 02:40 PM, Gabor wrote:



Now, a chip that had both setup and hold times that were negative --
that would be astounding.

--
Click to expand...
Kind of like precognitive sram. You get the data before you give it th
address.


I've used asic libraries that were "0-Hold" time and all they do is twea
the
timing with more delay in the D path than the C path. It's nice in that yo
don't have to fix hold times but most paths will have enough delay that
hold time fix is not needed. You then have to deal with the loss of setu
time that affects all flops and this makes it harder to meet timing.

John

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Jul 8, 9:21 am, "jt_eaton"
<z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On 07/07/2011 02:40 PM, Gabor wrote:

Now, a chip that had both setup and hold times that were negative --
that would be astounding.

--

Kind of like precognitive sram. You get the data before you give it the
address.

I've used asic libraries that were "0-Hold" time and all they do is tweak
the
timing with more delay in the D path than the C path. It's nice in that you
don't have to fix hold times but most paths will have enough delay that a
hold time fix is not needed. You then have to deal with the loss of setup
time that affects all flops and this makes it harder to meet timing.

John      

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
Sounds like everybody knows this but me... but now I think I can joint
the group
Thank you all very much, all the sudden I'm enlightenment, but please
correct me if I'm still in darkness :)))

This "negative hold time" (new to me) or whatever quantity, and the
setup time the two points will define a time window, in which data
can't be changed !
 
On Jul 8, 10:46 am, Mawa_fugo <cco...@netscape.net> wrote:
On Jul 8, 9:21 am, "jt_eaton"



z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On 07/07/2011 02:40 PM, Gabor wrote:

Now, a chip that had both setup and hold times that were negative --
that would be astounding.

--

Kind of like precognitive sram. You get the data before you give it the
address.

I've used asic libraries that were "0-Hold" time and all they do is tweak
the
timing with more delay in the D path than the C path. It's nice in that you
don't have to fix hold times but most paths will have enough delay that a
hold time fix is not needed. You then have to deal with the loss of setup
time that affects all flops and this makes it harder to meet timing.

John      

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Sounds like everybody knows this but me... but now I think I can joint
the group
Thank you all very much, all the sudden I'm enlightenment, but please
correct me if I'm still in darkness :)))

This "negative hold time" (new to me) or whatever quantity, and the
setup time the two points will define a time window, in which data
can't be changed !
Click to expand...
But the concept "you get the data before you give the memory the
address" is - not in my imagination
 
On 07/08/2011 08:51 AM, Mawa_fugo wrote:
On Jul 8, 10:46 am, Mawa_fugo<cco...@netscape.net> wrote:
On Jul 8, 9:21 am, "jt_eaton"



z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On 07/07/2011 02:40 PM, Gabor wrote:

Now, a chip that had both setup and hold times that were negative --
that would be astounding.

--

Kind of like precognitive sram. You get the data before you give it the
address.

I've used asic libraries that were "0-Hold" time and all they do is tweak
the
timing with more delay in the D path than the C path. It's nice in that you
don't have to fix hold times but most paths will have enough delay that a
hold time fix is not needed. You then have to deal with the loss of setup
time that affects all flops and this makes it harder to meet timing.

John

---------------------------------------
Posted throughhttp://www.FPGARelated.com

Sounds like everybody knows this but me... but now I think I can joint
the group
Thank you all very much, all the sudden I'm enlightenment, but please
correct me if I'm still in darkness :)))

This "negative hold time" (new to me) or whatever quantity, and the
setup time the two points will define a time window, in which data
can't be changed !
Click to expand...
Correct.

But the concept "you get the data before you give the memory the
address" is - not in my imagination
Click to expand...
It's a joke.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
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