Spartan3a: improving DCM performance and "To achieve optimal

[Philip Pemberton]

Hi guys,

Can anyone explain the following INFO alert I saw in my ISE build log?

INFOhysDesignRules:772 - To achieve optimal frequency synthesis
performance
with the CLKFX and CLKFX180 outputs of the DCM comp
clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet.

This is on a Spartan3a design which uses a DCM to multiply the incoming
25MHz clock up to 50MHz, then feeds it to another DCM which generates
CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz
clock. The 0deg clock is used to drive the CPU, SDRAM controller and
other stuff, while the 90deg clock is used to drive the SDRAM itself.

I've tried searching Xilinx's website for an "interactive datasheet" and
found nothing. This INFO alert caught my interest because I'd like to get
my design running a bit faster (66MHz would be nice, 75MHz or 100MHz even
better, the SDRAM tops out at 133MHz).

In theory a single-DCM design should be good to 133MHz (at least that's
what the timing report says), but as soon as I add the frequency synth,
the max frequency drops to 60MHz or so. Is there anything I can do to eek
a bit more speed out of this thing?

Thanks,
--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

 

[John McCaskill]

On Aug 10, 8:43 pm, Philip Pemberton <usene...@philpem.me.uk> wrote:

Hi guys,

Can anyone explain the following INFO alert I saw in my ISE build log?

INFOhysDesignRules:772 - To achieve optimal frequency synthesis
performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet.

This is on a Spartan3a design which uses a DCM to multiply the incoming
25MHz clock up to 50MHz, then feeds it to another DCM which generates
CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz
clock. The 0deg clock is used to drive the CPU, SDRAM controller and
other stuff, while the 90deg clock is used to drive the SDRAM itself.

I've tried searching Xilinx's website for an "interactive datasheet" and
found nothing. This INFO alert caught my interest because I'd like to get
my design running a bit faster (66MHz would be nice, 75MHz or 100MHz even
better, the SDRAM tops out at 133MHz).

In theory a single-DCM design should be good to 133MHz (at least that's
what the timing report says), but as soon as I add the frequency synth,
the max frequency drops to 60MHz or so. Is there anything I can do to eek
a bit more speed out of this thing?

Thanks,
--
Phil.
usene...@philpem.me.ukhttp://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

From your description, I assume that you have been using the CLK2X
output of a DCM to go from 25MHz to 50MHz and then cascade that to
another DCM to get the 0 and 90 degrees outputs, and now you want to
use the CLKFX instead to go a bit faster. Is that correct? If so, you
need to be aware that the CLKFX output of the DCM adds more jitter
than any of the other outputs.

I have not checked the S3A, but on the V4 the CLKFX adds too much
jitter to use it as the input to another DCM. Check the S3A data
sheet to see if that is the case for the S3A. Jitter adds root mean
square, so if the CLKFX jiiter is too much, see if you can cascade two
CLK2X DCM outputs and have less jitter. If so two CLK2X DCM outputs
cascaded with a 1.5 CLKDV output would get you 66.66... MHz

Regards,

John McCaskill
www.FasterTechnology.com

 

[Philip Pemberton]

On Tue, 10 Aug 2010 19:58:35 -0700, John McCaskill wrote:

From your description, I assume that you have been using the CLK2X
output of a DCM to go from 25MHz to 50MHz and then cascade that to
another DCM to get the 0 and 90 degrees outputs, and now you want to use
the CLKFX instead to go a bit faster. Is that correct?

Sorry -- I should have been more clear about this. I'm using the first
DCM's CLKFX output to drive the second DCM's clock input, then the main
control logic gets CLK0 from DCM#2, and the SDRAM gets CLK90 from DCM#2.

The best clock rate I've managed to get out of it is CLK0 = 50MHz, and
the timing report says the best I should expect is about 63MHz. I'd just
like to get that up to around 75MHz or so...

I have not checked the S3A, but on the V4 the CLKFX adds too much jitter
to use it as the input to another DCM. Check the S3A data sheet to see
if that is the case for the S3A.

Ah -- I didn't realise that; I'll check the datasheet. Is there an
explicit statement in the V4 datasheet about this, or just a subtle note
buried in a data table?

Jitter adds root mean square, so if
the CLKFX jiiter is too much, see if you can cascade two CLK2X DCM
outputs and have less jitter. If so two CLK2X DCM outputs cascaded with
a 1.5 CLKDV output would get you 66.66... MHz

Thanks for the suggestion -- I'll try that when I get a few minutes. At
the moment I'm trying to graft my new SDRAM controller core onto my
Latticemico32 SoC (and not having much success).

--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

 

[maxascent]

Phil, what board are you using? Cant you just swap the oscillator for
faster one?

Jon

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Philip Pemberton]

On Thu, 12 Aug 2010 03:20:59 -0500, maxascent wrote:

Phil, what board are you using? Cant you just swap the oscillator for a
faster one?

An Enterpoint Drigmorn2.

The oscillator is a tiny little SMD thing, enclosed on one side by the
SDRAM chip and on the other by a large SMD capacitor. Replacing it with
something else would involve a fair amount of careful SMD rework... not
something I'm keen on doing to a ÂŁ120 development board.

Wiring a tin-can oscillator up to one of the GPIOs wouldn't be hard,
though I don't have any 66MHz or 75MHz tin-cans in my spares box

--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

 

[John_H]

On Aug 12, 9:42 am, Philip Pemberton <usene...@philpem.me.uk> wrote:

On Thu, 12 Aug 2010 03:20:59 -0500, maxascent wrote:
Phil, what board are you using? Cant you just swap the oscillator for a
faster one?

An Enterpoint Drigmorn2.

The oscillator is a tiny little SMD thing, enclosed on one side by the
SDRAM chip and on the other by a large SMD capacitor. Replacing it with
something else would involve a fair amount of careful SMD rework... not
something I'm keen on doing to a Ł120 development board.

Wiring a tin-can oscillator up to one of the GPIOs wouldn't be hard,
though I don't have any 66MHz or 75MHz tin-cans in my spares box

--
Phil.
usene...@philpem.me.ukhttp://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

Then there's the idea of using a 100 MHz clock from the CLKFX output
and using clock enables to select the main clock or the 90 degree (at
50MHz) version.

 

[Andy Peters]

On Aug 10, 6:43 pm, Philip Pemberton <usene...@philpem.me.uk> wrote:

Hi guys,

Can anyone explain the following INFO alert I saw in my ISE build log?

INFOhysDesignRules:772 - To achieve optimal frequency synthesis
performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   clock_generator/DCM_SP_INST, consult the device Interactive Data Sheet.

This is on a Spartan3a design which uses a DCM to multiply the incoming
25MHz clock up to 50MHz, then feeds it to another DCM which generates
CLK0 and CLK90 (0 and 90 degree phase-shifted clocks) from the 50MHz
clock. The 0deg clock is used to drive the CPU, SDRAM controller and
other stuff, while the 90deg clock is used to drive the SDRAM itself.

I get this same exact warning on every design which uses the DCM's
clock synthesizer (CLKFX) output in any Xilinx FPGA family. It shows
up even when there is just one DCM, no cascading, nothing special.

It's another example of Xilinx lossage.

Open a WebCase and see if they can explain it to you!

-a