Spartan3 multiplier

[Theron Hicks]

Hello,
Can anyone give me an approximate time for an 18 by 18 multiply using
the spartan3. I cannot seem to find a specification for this in the data
sheet. I realize that the time is a function of the number of bits. Also,
I assume that this multiplier is not clocked. In otherwords, does the value
eventually ripple through to the output, or is this system in some fashion
clocked. An input latch is quite acceptable, I just would rather not deal
with a clocked delay through the multiplier.
Thanks,
Theron

 

[Uwe Bonnes]

Theron Hicks <hicksthe@egr.msu.edu> wrote:
: Hello,
: Can anyone give me an approximate time for an 18 by 18 multiply using
: the spartan3. I cannot seem to find a specification for this in the data
: sheet. I realize that the time is a function of the number of bits. Also,
: I assume that this multiplier is not clocked. In otherwords, does the value
: eventually ripple through to the output, or is this system in some fashion
: clocked. An input latch is quite acceptable, I just would rather not deal
: with a clocked delay through the multiplier.

Look at the Virtex datasheet to get a feeling of the multiplier behaviour.

--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Steven K. Knapp]

The worst-case delay in a 18-bit x18-bit =36-bit multiply is from bit 0 of
the input to bit 35 of the product. Using the -4 speed grade, which is the
slowest, this delay is reported as 7.98 ns.

If your application can tolerate a few clock cycles of extra latency, then
you can fully pipeline the multiplier (registered input, pipelined
multiplier, registered output) and operate at ~150 MHz using the techniques
described in application note XAPP636.

Here are two application note references that may be of interest.

XAPP467: Using Embedded Multipliers in Spartan-3 FPGAs
http://www.xilinx.com/xapp/xapp467.pdf

XAPP636: Optimal Pipelining of the I/O Ports of Virtex-II Multipliers
http://www.xilinx.com/xapp/xapp636.pdf
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:bjfpov$278v$1@msunews.cl.msu.edu...

Hello,
Can anyone give me an approximate time for an 18 by 18 multiply using
the spartan3. I cannot seem to find a specification for this in the data
sheet. I realize that the time is a function of the number of bits.
Also,
I assume that this multiplier is not clocked. In otherwords, does the
value
eventually ripple through to the output, or is this system in some fashion
clocked. An input latch is quite acceptable, I just would rather not deal
with a clocked delay through the multiplier.
Thanks,
Theron