Spartan III I/O robustness

[lecroy]

I was not able to find a way to continue the old thread (too old??),
but my basic question was:

I have spent the last 60 days trying to get an answer from Xilinx on
their new S3 devices. During a review, it was stated that the new S3s
were very sensitive to transients on the I/O pins. Because they made a
point to mention this during the review, I posed the following
question to Xilinx:

"If we look at the incident versus reflected energy and tune the stub
(trace)
for a worst case match is it possible the driver could be damaged or
the
chip lock up due to the reflected energy?"

"The circuit would be as follows:
Spartan III Output ------------------------------ Tunable Stub"

I wonder if anyone in this group has asked this question and what was
the responce from Xilinx?

Just do a search for reflected in the comp.arch.fpga group and you
should find the entire thread, or try:

http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&th=49df88f46d6fa0ff&rnum=2


I just got this information that may be of interest to some of you.

Subject: Spartan 3E / 4 information
Apparently the problem with past parts was that the I/O was really
2.5V so when >boosting up to 3.3 already took away most of the

overshoot window. This new

revision should correct this. I believe this is preliminary info, but
yes this >is meant to resolve the reflected signal issue. Apparently

this issue is also >in other parts, I believe the Virtex II.


What I find interesting is that after all the feedback from Xilinx on
this subject that they may change the technology to address this
concern.

 

[Steven K. Knapp]

"lecroy" <lecroy7200@chek.com> wrote in message
news:9297c711.0408100454.3612bf68@posting.google.com...
[snip]

"If we look at the incident versus reflected energy and tune the stub
(trace) for a worst case match is it possible the driver could be
damaged or the chip lock up due to the reflected energy?"

"The circuit would be as follows:
Spartan III Output ------------------------------ Tunable Stub"

I wonder if anyone in this group has asked this question and what was
the responce from Xilinx?

[snip]

I just got this information that may be of interest to some of you.

Apparently the problem with past parts was that the I/O was really
2.5V so when boosting up to 3.3 already took away most of the
overshoot window. This new revision should correct this. I believe
this is preliminary info, but yes this is meant to resolve the reflected
signal issue. Apparently this issue is also in other parts, I believe the
Virtex II.

Sorry I missed this one the first time around. Some of the confusion might
be due to initial early Spartan-3 FPGA engineering samples that did not
officially support 3.3V I/O. The Spartan-3 FPGAs available today do support
3.3V I/O.

Xilinx recommends limiting overshoot/undershoot to less than 500 mV so as
not to turn on the I/O protection diodes. Consequently, the recommended
voltage at the I/O pad should never be lower than 0.5V or more than
VCCO+0.5V. In all the HyperLynx IBIS board simulations that I've done, I've
never seen a case where the output created a voltage that it could not
tolerate. Certainly, the destinations may see a higher voltage depending on
I/O drive strength and trace length. Consequently, you may need to
terminate the signal for the voltage on the receiving end. That said, there
may be some sort of pathological case that I have not seen in practical
designs.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC

 

[lecroy]

Just thought I would post the remainder of the conversation. Hope it
helps some of you. Also, if anyone has the orignal documents that
call out the 10% matching, could you pass this on to Steve or post it.


Most recent first.

Steve,

Was the 10% matching based on the 300 mV numbers?
I'm not sure from where that value originated.

Prior to the S3 being released I saw a presentation on it. The 10%
caught my attention. I asked for a copy of the slides but they would

not release them. Later I found this same specification called out in
one of the application notes. I did a quick search, but it appears
Xilinx has changed many of these documents several times over from
that
time and there is no mention of the matching. On the plus side, I
think I may have kept my orignal copies at home. I will see if I can
dig them up and pass them onto you.

Ahhh, that could be. The official Xilinx word on I/O robustness, I
think, was overly conservative until the actual process qualification
was complete. Some of the early values were indeed extremely
limiting.

I'd still be interested if you come across those documents, just to
make
sure we purge the old data.

Thanks.



Hi Anonymous,

Question: Do you happen to go by another name? Why the anonymity? I
promise, I don't bite.

From the thread:

"Steve, From the document you will notice that the concern is with
matching inputs. They are asking for an impedance match of less than

10%. My question is about the reflected energy from a driver to a
poorly terminated load. So, if we look at the incident versus
reflected
energy and tune the stub (trace) for a worst case match is it possible
the driver could be damaged or the chip lock up due to the reflected
energy?"

That 10% could easily be eaten up by the layout, PCB processing or
simulation. So, while your simulation may be showing you one thing,

to
meet this 10% is going to take a "real" board and a VNA to verify. If
we have a mismatch of say 12%, how does that effect the life of the
part? What drove the designers to 10% limit?

Sorry, I've been reading through the volumous thread. I did note that
the thread has some old information. Back when the question was
asked,
we hadn't yet completed all our process qualification steps and the
engineers asked us to keep the input voltage to 3.75V or less, with
total overshoot of +/-300 mV. This has since been relaxed to +/-500
mV,
with an absolute maximum voltage of 4.05V.

Was the 10% matching based on the 300 mV numbers? I'm not sure from
where that value originated.

In the diagram that I sent, there is a small amount of time where the
voltage on the input exceeds 4.05V. Above this voltage, there is the
possibility of a long-term wear out mechanism called Time Dependent
Dielectric Breakdown (TDDB). Voltages above 4.05V will not
immediately
cause the device to fail and it will not cause the chip to lock up.
Essentially, you will see the output leak more and more current until
it
eventually fails. The time to failure depends on the magnitude of the
overvoltage and the duration.

Does this help at all with your original question? Is there
additional
information that you would like.
---------------------------------


Hi Anonymous and Hal,

The last comment from Xilinx was "Going back to your original
question, the answer back from the factory is at
3.3 V signaling, it is possible to have reflections damage the part.".
This was followed by several posts about the importance of simulation.

Based on your initial question, I tried a few simulations using some
pathological conditions and, yes, it is possible to exceed the
Absolute
Maximum Ratings listed in the data sheet. For example, if you use the
biggest, fastest output available (LVCMOS_FAST_24mA), operate it at
maximum voltage (VCCO=3.45V), run it down a long trace (100 cm),
simulate it under worst-case conditions, to an high-impedance load,
you
can exceed 4.05V absolute maximum rating at the Spartan-3 FPGA output
for about 1 ns. Add a 33 ohm source termination resistor or reduce
the
trace length to 15 cm and you easily fall within the recommended
VCCO+/-0.5V range. Similar effects are possible using a different I/O
standard. I purposely picked the biggest current drive output with
the
fastest switching edges and used the Fast-Strong simulation model
(worst-case to generate maximum overshoot/undershoot).

In every PCB simulation that I've done so far, and certainly the scope
shots from actual silicon, look better than this. IBIS provides an
excellent first-order approximation of the actual results. However,
this simple analysis isn't modeling packaging loads, etc.

Attached is a PDF showing the results.

I also checked with Xilinx design engineering. Before device
qualification was complete, they wanted to limit the recommended
maximum
voltage on the inputs to no more than 3.75V (VCCO+0.3V). This has
since
been relaxed to VCCO+0.5V, or 3.95V.

Please let me know if this answers your question or not.

 

[Austin Lesea]

?,

Is there a question here that I could answer for someone?

It is unclear what is being asked.

DCI accuracy? IO SI issues with 3.3V and the 4.05 V abs max
specification? What happens if the IO spends time at and beyond the
4.05V gate stress abs max limits?

I can answer any, or all if anyone wants to know.

The answers will also apply to VII Pro, Pro-X, S3, and V4 (as they all
use 0.25u IO transistors).

Austin



lecroy wrote:

Just thought I would post the remainder of the conversation. Hope it
helps some of you. Also, if anyone has the orignal documents that
call out the 10% matching, could you pass this on to Steve or post it.


Most recent first.



Steve,


Was the 10% matching based on the 300 mV numbers?
I'm not sure from where that value originated.

Prior to the S3 being released I saw a presentation on it. The 10%

caught my attention. I asked for a copy of the slides but they would
not release them. Later I found this same specification called out in
one of the application notes. I did a quick search, but it appears
Xilinx has changed many of these documents several times over from
that
time and there is no mention of the matching. On the plus side, I
think I may have kept my orignal copies at home. I will see if I can
dig them up and pass them onto you.

Ahhh, that could be. The official Xilinx word on I/O robustness, I
think, was overly conservative until the actual process qualification
was complete. Some of the early values were indeed extremely
limiting.

I'd still be interested if you come across those documents, just to
make
sure we purge the old data.

Thanks.



Hi Anonymous,

Question: Do you happen to go by another name? Why the anonymity? I
promise, I don't bite.


From the thread:

"Steve, From the document you will notice that the concern is with

matching inputs. They are asking for an impedance match of less than
10%. My question is about the reflected energy from a driver to a
poorly terminated load. So, if we look at the incident versus
reflected
energy and tune the stub (trace) for a worst case match is it possible
the driver could be damaged or the chip lock up due to the reflected
energy?"



That 10% could easily be eaten up by the layout, PCB processing or

simulation. So, while your simulation may be showing you one thing,
to
meet this 10% is going to take a "real" board and a VNA to verify. If
we have a mismatch of say 12%, how does that effect the life of the
part? What drove the designers to 10% limit?

Sorry, I've been reading through the volumous thread. I did note that
the thread has some old information. Back when the question was
asked,
we hadn't yet completed all our process qualification steps and the
engineers asked us to keep the input voltage to 3.75V or less, with
total overshoot of +/-300 mV. This has since been relaxed to +/-500
mV,
with an absolute maximum voltage of 4.05V.

Was the 10% matching based on the 300 mV numbers? I'm not sure from
where that value originated.

In the diagram that I sent, there is a small amount of time where the
voltage on the input exceeds 4.05V. Above this voltage, there is the
possibility of a long-term wear out mechanism called Time Dependent
Dielectric Breakdown (TDDB). Voltages above 4.05V will not
immediately
cause the device to fail and it will not cause the chip to lock up.
Essentially, you will see the output leak more and more current until
it
eventually fails. The time to failure depends on the magnitude of the
overvoltage and the duration.

Does this help at all with your original question? Is there
additional
information that you would like.
---------------------------------


Hi Anonymous and Hal,


The last comment from Xilinx was "Going back to your original

question, the answer back from the factory is at

3.3 V signaling, it is possible to have reflections damage the part.".

This was followed by several posts about the importance of simulation.




Based on your initial question, I tried a few simulations using some
pathological conditions and, yes, it is possible to exceed the
Absolute
Maximum Ratings listed in the data sheet. For example, if you use the
biggest, fastest output available (LVCMOS_FAST_24mA), operate it at
maximum voltage (VCCO=3.45V), run it down a long trace (100 cm),
simulate it under worst-case conditions, to an high-impedance load,
you
can exceed 4.05V absolute maximum rating at the Spartan-3 FPGA output
for about 1 ns. Add a 33 ohm source termination resistor or reduce
the
trace length to 15 cm and you easily fall within the recommended
VCCO+/-0.5V range. Similar effects are possible using a different I/O
standard. I purposely picked the biggest current drive output with
the
fastest switching edges and used the Fast-Strong simulation model
(worst-case to generate maximum overshoot/undershoot).

In every PCB simulation that I've done so far, and certainly the scope
shots from actual silicon, look better than this. IBIS provides an
excellent first-order approximation of the actual results. However,
this simple analysis isn't modeling packaging loads, etc.

Attached is a PDF showing the results.

I also checked with Xilinx design engineering. Before device
qualification was complete, they wanted to limit the recommended
maximum
voltage on the inputs to no more than 3.75V (VCCO+0.3V). This has
since
been relaxed to VCCO+0.5V, or 3.95V.

Please let me know if this answers your question or not.

 

[Luiz Carlos]

Hi Austin,

Spartan3 suports 5V using external resistors.
So, I suppose I can also use a resistor for interface a signal that
swings from -18V to +18V. Ok? There are internal diodes to VCC and
GND, isn't it?

Luiz Carlos.

 

[Austin Lesea]

Luiz,

Yes, absolutely.

Examine the ASCII IBIS file and you will directly see the IV curve of
the protection (clamp) diodes to ground, and Vcco.

Select your resistor value such that the current is less than 10 mA into
the diodes, and everything is just fine.

Austin

Luiz Carlos wrote:

Hi Austin,

Spartan3 suports 5V using external resistors.
So, I suppose I can also use a resistor for interface a signal that
swings from -18V to +18V. Ok? There are internal diodes to VCC and
GND, isn't it?

Luiz Carlos.