Y
Yury
Guest
Greetings,
here is an interesting problem: ISE 4.2i, ISE 5.2i SP3 - same result,
Slave Serial configuation of Spartan-IIE 300 results in un-intended
(erroneous) functionality, while JTAG configuation based on the same
..ncd file results in proper functionality.
The FPGA gets "properly" configured in either case (PROGRAM, INIT and
DONE lines do what they supposed to) - DONE goes high. For JTAG
configuration a .bit file is generated using JTAG startup clock
option, while for Slave Serial - CCLK startup clock option is used in
BITGEN command line.
When JTAG port is used to verify the contents of the FPGA (against
..bit file that results in proper functionality) after is was
configured using slave serial approach (resulting in erroneous
functionality) - the verification is reported as a success!!!
Anyone have seen anything like that? Any suggestions?
Thanks for any help.
-- YWS
here is an interesting problem: ISE 4.2i, ISE 5.2i SP3 - same result,
Slave Serial configuation of Spartan-IIE 300 results in un-intended
(erroneous) functionality, while JTAG configuation based on the same
..ncd file results in proper functionality.
The FPGA gets "properly" configured in either case (PROGRAM, INIT and
DONE lines do what they supposed to) - DONE goes high. For JTAG
configuration a .bit file is generated using JTAG startup clock
option, while for Slave Serial - CCLK startup clock option is used in
BITGEN command line.
When JTAG port is used to verify the contents of the FPGA (against
..bit file that results in proper functionality) after is was
configured using slave serial approach (resulting in erroneous
functionality) - the verification is reported as a success!!!
Anyone have seen anything like that? Any suggestions?
Thanks for any help.
-- YWS