[Spartan-IIE] Exeeding max. input rise/fall time of signals

[Markus Meng]

Hi all,

I would like know from the experts if the following behavior is possible
if the input signal rise is exeeded. Xilinx states in its datasheet it shall
be
no more than 250 ns.

If it is for exemaple 350 ns, but still - single pole - monotonic rise time,
what
is the internal logic seeing? Is it possible that the transistion
from "0-1" is being seen as something like "0-1-0-1", or is only a matter of
power consumption in the CMOS input stage, or even something else?

Best Regards
Markus

 

[jim granville]

Markus Meng wrote:

Hi all,

I would like know from the experts if the following behavior is possible
if the input signal rise is exeeded. Xilinx states in its datasheet it shall
be
no more than 250 ns.

If it is for exemaple 350 ns, but still - single pole - monotonic rise time,
what
is the internal logic seeing? Is it possible that the transistion
from "0-1" is being seen as something like "0-1-0-1", or is only a matter of
power consumption in the CMOS input stage, or even something else?

Both.
Slow slew IPs will certainly increase the power, due to more time in the
linear region.
They can also cause double clocking, and you can get some feel for this
by adding some finite ground bounce.
eg a 3.5V slev in 350ns is 10V/us, or 100mv in 10ns.
Thus, if a consequent OP,( or many buried nodes ) change within 10ns,
and this causes 100mv of ground movement, then you get double-clocking
effects.
Hysteresis will help, but does _not_ guarantee to eliminate this - it
gives a threshold to the tolerable system bounce.
Carefull design is still needed to ensure you stay comfortably under
that.

What Hysteresis _does_ reduce greatly, is threshold oscillation - the
effect where the CMOS inverter chain actually oscillates whilst in the
linear region - this oscillation is typ very fast, above the clock
MAX, but it can cause strange effects in even 'unrelated' logic.
Mention this to a digitial designer, and mostly you get a blank stare

-jg

 

[Peter Alfke]

"Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:<3fede218_1@news.bluewin.ch>...

Hi all,

I would like know from the experts if the following behavior is possible
if the input signal rise is exeeded. Xilinx states in its datasheet it shall
be
no more than 250 ns.

If it is for exemaple 350 ns, but still - single pole - monotonic rise time,
what
is the internal logic seeing? Is it possible that the transistion
from "0-1" is being seen as something like "0-1-0-1", or is only a matter of
power consumption in the CMOS input stage, or even something else?

Best Regards
Markus

In the absence of noise ( if there were such a condition), there is no
limit to the rise/fall time, but you would still have to face the
large timing uncertainty.

For combinatorial inputs, there never is a transition-time limit ( but
you have to live with the timing uncertainty...)
For clocks, any transition time of more than 10 ns is objectionable,
since it can result in double-triggering caused by ground-bounce and
general noise in the system (plus the timing uncertainty).

The suspected increase in power consumption is really insignificant,
less than 5 mA during less than 10% of the transition time. No big
deal.

Peter Alfke, Xilinx Applications

 

[jim granville]

Peter Alfke wrote:

In the absence of noise ( if there were such a condition), there is no
limit to the rise/fall time, but you would still have to face the
large timing uncertainty.

For combinatorial inputs, there never is a transition-time limit ( but
you have to live with the timing uncertainty...)

This is true only for an ideal (viz : non real, 0nH ) device.
If transistion oscillations occur (and they are common on
non schmitt, CMOS chained inverter structures), then
even combin IPs can affect other seemingly unrelated logic.

-jg

 

[Peter Alfke]

All Xilinx FPGAs have input hysteresis (Schmitt triggered inputs).
Peter Alfke

jim granville <no.spam@designtools.co.nz> wrote in message news:<N%vHb.14744$ws.1502122@news02.tsnz.net>...

Peter Alfke wrote:
In the absence of noise ( if there were such a condition), there is no
limit to the rise/fall time, but you would still have to face the
large timing uncertainty.

For combinatorial inputs, there never is a transition-time limit ( but
you have to live with the timing uncertainty...)

This is true only for an ideal (viz : non real, 0nH ) device.
If transistion oscillations occur (and they are common on
non schmitt, CMOS chained inverter structures), then
even combin IPs can affect other seemingly unrelated logic.

-jg

 

[Uwe Bonnes]

Peter Alfke <palfke@earthlink.net> wrote:
: All Xilinx FPGAs have input hysteresis (Schmitt triggered inputs).
: Peter Alfke

Is this hysteresis spec'ed somewhere?
For example, in ds001 (full Spartan II datasheet) I can't find any occurance
of "hyst".

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Peter Alfke]

I also could not find the specification ( and there is a limited crew around in
these days).
But I know that the hysteresis depends on the I/O standard and the part family.

If you want to investigate, it's very simple:
Take the input and bring it out, inverted, on a pin that is not adjacent.
Then connect a large resistor from the output to the input ( 10 kilohm ) and
decouple the input to ground with a big capacitor ( 10 nF). Now you have an
oscillator, and the voltage on the input, (i.e. the capacitor) oscillates
between the two hysteresis points.
That's how them old folks used to build oscillators with a 7414...
Happy New Year!
Peter Alfke
==============================

 

[Ray Andraka]

Quite possible. A slow moving signal can actually get the input to oscillate
due to the input threshold changing slightly when the input buffer's output
state is changed. Noise on the reference can also do that if the signal is
hanging around the threshold region. Put some hysteresis on the input or use a
schmitt trigger to clean it up.

Markus Meng wrote:

Hi all,

I would like know from the experts if the following behavior is possible
if the input signal rise is exeeded. Xilinx states in its datasheet it shall
be
no more than 250 ns.

If it is for exemaple 350 ns, but still - single pole - monotonic rise time,
what
is the internal logic seeing? Is it possible that the transistion
from "0-1" is being seen as something like "0-1-0-1", or is only a matter of
power consumption in the CMOS input stage, or even something else?

Best Regards
Markus

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
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