J
Jerker Hammarberg (DST)
Guest
Hello! I'm trying to configure two Spartan IIE (XC2S300E) in a daisy chain
using two PROMs (XC18V02) but I cannot seem to make any configuration data
reach the second (slave) FPGA. As a result, the DONE pin will be held low by
the second FPGA and the system will never start.
That was the short version, here is the long one: The four components, two
XC18V02 and two XC2S300E, are connected exactly according to figure 5 in the
XC18V00 data sheet, that is:
* /CF of both PROMs are connected to /PROGRAM of both FPGAs
* DONE of both FPGAs are connected to /CE of first PROM
* /CEO of first PROM is connected to /CE of second PROM
* INIT of both FPGAs are connected to /RESET of both PROMs
* D0 of both PROMs are connected to DIN of master FPGA
* DOUT of master FPGA is connected to DIN of slave FPGA
* CCLK of master FPGA is connected to CLK of both PROMs and to CCLK of slave
FPGA.
So at power up, I expect the following:
1. Both FPGAs pull DONE low, enabling first PROM.
2. Both FPGAs release /INIT when initialization is done, the wire is pulled
up and /RESET on both PROMs go high.
3. First PROM sends data from D0 to DIN of master FPGA, clocked by CCLK of
master FPGA.
4. When done, /CEO of first PROM goes low, enabling second PROM. At the same
time, master FPGA releases the DONE pin; however, slave FPGA keeps it down
since it is not yet configured.
5. Second PROM sends data from D0 to DIN of master FPGA, which should
forward the data from its DOUT into DIN of slave FPGA.
6. When done, slave FPGA should release DONE, the wire should be pulled up
and both FPGAs should go into normal function.
Things go wrong at step 5. The problem is that master FPGA never forwards
any data. In fact, DOUT is high constantly as soon as power is on. Having
read some earlier posts, I think that DOUT should not only copy all bits
dedicated for slave FPGA at step 5, but it should also present the first 32
or 40 synchronization bits when master FPGA itself is being configured at
step 3. This doesn't happen either. Anyone has any ideas about what is
wrong? Does the above description make sense, or have I misunderstood
anything?
Here are some more clues:
* We use Xilinx iMPACT for configuration. DONE and /INIT are both pulled up
by 3.3kOhm resistors, but we have also tried 4.7kOhm.
* We have two boards to experiment with and the same thing happens with both
boards, so it's unlikely that there's something wrong with the FPGAs.
* When disconnecting the DONE pin of slave FPGA, the DONE wire goes high
after configuration of master FPGA, which works fine afterwards.
* The MODE pins are actively held 000 on master and 111 on slave.
Thanks in advance!
/Jerker
using two PROMs (XC18V02) but I cannot seem to make any configuration data
reach the second (slave) FPGA. As a result, the DONE pin will be held low by
the second FPGA and the system will never start.
That was the short version, here is the long one: The four components, two
XC18V02 and two XC2S300E, are connected exactly according to figure 5 in the
XC18V00 data sheet, that is:
* /CF of both PROMs are connected to /PROGRAM of both FPGAs
* DONE of both FPGAs are connected to /CE of first PROM
* /CEO of first PROM is connected to /CE of second PROM
* INIT of both FPGAs are connected to /RESET of both PROMs
* D0 of both PROMs are connected to DIN of master FPGA
* DOUT of master FPGA is connected to DIN of slave FPGA
* CCLK of master FPGA is connected to CLK of both PROMs and to CCLK of slave
FPGA.
So at power up, I expect the following:
1. Both FPGAs pull DONE low, enabling first PROM.
2. Both FPGAs release /INIT when initialization is done, the wire is pulled
up and /RESET on both PROMs go high.
3. First PROM sends data from D0 to DIN of master FPGA, clocked by CCLK of
master FPGA.
4. When done, /CEO of first PROM goes low, enabling second PROM. At the same
time, master FPGA releases the DONE pin; however, slave FPGA keeps it down
since it is not yet configured.
5. Second PROM sends data from D0 to DIN of master FPGA, which should
forward the data from its DOUT into DIN of slave FPGA.
6. When done, slave FPGA should release DONE, the wire should be pulled up
and both FPGAs should go into normal function.
Things go wrong at step 5. The problem is that master FPGA never forwards
any data. In fact, DOUT is high constantly as soon as power is on. Having
read some earlier posts, I think that DOUT should not only copy all bits
dedicated for slave FPGA at step 5, but it should also present the first 32
or 40 synchronization bits when master FPGA itself is being configured at
step 3. This doesn't happen either. Anyone has any ideas about what is
wrong? Does the above description make sense, or have I misunderstood
anything?
Here are some more clues:
* We use Xilinx iMPACT for configuration. DONE and /INIT are both pulled up
by 3.3kOhm resistors, but we have also tried 4.7kOhm.
* We have two boards to experiment with and the same thing happens with both
boards, so it's unlikely that there's something wrong with the FPGAs.
* When disconnecting the DONE pin of slave FPGA, the DONE wire goes high
after configuration of master FPGA, which works fine afterwards.
* The MODE pins are actively held 000 on master and 111 on slave.
Thanks in advance!
/Jerker